參數(shù)資料
型號: MAX1196ECM+D
廠商: Maxim Integrated Products
文件頁數(shù): 6/23頁
文件大?。?/td> 0K
描述: IC ADC 8BIT 40MSPS DL 48-TQFP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 250
位數(shù): 8
采樣率(每秒): 40M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 108mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP 裸露焊盤
供應商設備封裝: 48-TQFP 裸露焊盤(7x7)
包裝: 托盤
輸入數(shù)目和類型: 4 個單端,雙極;2 個差分,雙極
MAX1196
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
14
______________________________________________________________________________________
tDOB
tCL
tCH
tCLK
tDOA
tDA/B
5 CLOCK-CYCLE LATENCY (CHA), 5.5 CLOCK-CYCLE LATENCY (CHB)
A/B
CHB
D0A/B–D7A/B
D0B
CHA
D1A
CHB
D1B
CHA
D2A
CHB
D2B
CHA
D3A
CHB
D3B
CHA
D4A
CHB
D4B
CHA
D5A
CHB
D5B
CHA
D6A
CHB
D6B
CHA
CHB
CLK
Figure 3. System Timing Diagram
and REFN are outputs. REFOUT can be left open or
connected to REFIN through a >10k
resistor.
In unbuffered external reference mode, connect REFIN
to GND. This deactivates the on-chip reference buffers
for REFP, COM, and REFN. With their buffers shut down,
these nodes become high-impedance inputs and can be
driven through separate, external reference sources.
For detailed circuit suggestions and how to drive this
dual ADC in buffered/unbuffered external reference
mode, see the Applications Information section.
Clock Input (CLK)
The MAX1196’s CLK input accepts CMOS-compatible
clock signal. Since the interstage conversion of the
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low
jitter and fast rise and fall times (<2ns). In particular,
sampling occurs on the rising edge of the clock signal,
requiring this edge to provide lowest possible jitter. Any
significant aperture jitter would limit the SNR perfor-
mance of the on-chip ADCs as follows:
where fIN represents the analog input frequency and
tAJ is the time of the aperture jitter.
Clock jitter is especially critical for undersampling
applications. The clock input should always be consid-
ered as an analog input and routed away from any ana-
log input or other digital signal lines.
The MAX1196 clock input operates with a voltage
threshold set to VDD/2. Clock inputs with a duty cycle
other than 50%, must meet the specifications for high
and low periods as stated in the Electrical
Characteristics.
System Timing Requirements
Figure 3 shows the relationship between clock and
analog input, A/B indicator, and the resulting valid
CHA/CHB data output. CHA and CHB data are sam-
pled on the rising edge of the clock signal. Following
the rising edge of the 5th clock cycles, the digitized
value of the original CHA sample is presented at the
output, followed one-half clock cycle later by the digi-
tized value of the original CHB sample.
A channel selection signal (A/B indicator) allows the
user to determine which output data represents which
input channel. With A/B = 1, digitized data from CHA is
present at the output and with A/B = 0 digitized data
from CHB is present.
SNR
ft
IN
AJ
log
××
×
20
1
2
π
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MAX1197ECM+TD 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8-Bit 2Ch 60Msps 3V High Speed ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX1197ECM-D 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32