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參數(shù)資料
| 型號： | MAX1183 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Dual 10-Bit, 40Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs |
| 中文描述： | 雙路、10位、40Msps、3V、低功耗ADC，內(nèi)置電壓基準(zhǔn)及并行輸出 |
| 文件頁數(shù)： | 4/18頁 |
| 文件大小： | 495K |
| 代理商： | MAX1183 |
M
Dual 10-Bit, 40Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +3V, OV
DD
= +2.5V, 0.1μF and 1.0μF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through
a 10k
resistor, V
IN
= 2Vp-p (differential with respect to COM), C
L
= 10pF at digital outputs (Note 5), f
CLK
= 40MHz, T
A
= T
MIN
to
T
MAX
, unless otherwise noted. Typical values are at T
A
= +25
°
C.)
PARAMETER
SYMBOL
CONDITIONS
DIGITAL INPUTS (CLK, PD,
OE
, SLEEP, T/B)
MIN
TYP
MAX
UNITS
CLK
0.8 x
V
DD
0.8 x
OV
DD
Input High Threshold
V
IH
PD,
OE
, SLEEP, T/B
V
CLK
0.2 x
V
DD
0.2 x
OV
DD
Input Low Threshold
V
IL
PD,
OE
, SLEEP, T/B
V
Input Hysteresis
V
HYST
I
IH
I
IL
C
IN
0.1
V
V
IH
= OV
DD
or V
DD
(CLK)
V
IL
= 0
±5
±5
Input Leakage
μA
Input Capacitance
DIGITAL OUTPUTS (D9A
–
D0A, D9B
–
D0B)
Output Voltage Low
5
pF
V
OL
I
SINK
= -200μA
0.2
V
Output Voltage High
V
OH
I
SOURCE
= 200μA
OV
DD
- 0.2
V
Three-State Leakage Current
Three-State Leakage
Capacitance
POWER REQUIREMENTS
Analog Supply Voltage Range
Output Supply Voltage Range
I
LEAK
OE
= OV
DD
±10
μA
C
OUT
OE
= OV
DD
5
pF
V
DD
OV
DD
2.7
1.7
3
3.6
3.6
60
V
V
2.5
40
2.8
1
Operating, f
INA or B
= 20MHz at -0.5dB FS
Sleep mode
Shutdown, clock idle, PD =
OE
= OV
DD
Operating, C
L
= 15pF,
f
INA or B
= 20MHz at -0.5dB FS
Sleep mode
Shutdown, clock idle, PD =
OE
= OV
DD
Operating, f
INA or B
= 20MHz at -0.5dB FS
Sleep mode
Shutdown, clock idle, PD =
OE
= OV
DD
Offset
Gain
mA
Analog Supply Current
I
VDD
15
μA
5.8
mA
100
2
120
8.4
3
±0.2
±0.1
Output Supply Current
I
OVDD
10
180
μA
mW
Power Dissipation
PDISS
45
μW
mV/V
%V
Power-Supply Rejection
PSRR
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
Output Enable Time
Output Disable Time
t
DO
Figure 3 (Note 3)
Figure 4
Figure 4
5
10
1.5
8
ns
ns
ns
t
ENABLE
t
DISABLE
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