參數資料
型號: MAX1169CEUD+T
廠商: Maxim Integrated Products
文件頁數: 17/20頁
文件大?。?/td> 0K
描述: IC ADC 16BIT 58.6KSPS 14-TSSOP
標準包裝: 2,500
位數: 16
采樣率(每秒): 58.6k
數據接口: I²C,串行
轉換器數目: 1
功率耗散(最大): 864mW
電壓電源: 模擬和數字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 14-TSSOP
包裝: 帶卷 (TR)
輸入數目和類型: 8 個單端,單極
MAX1169
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
6
_______________________________________________________________________________________
Note 9: A master device must provide a data hold time for SDA (referred to VIL of SCL) in order to bridge the undefined region of
SCL’s falling edge (see Figure 1).
Note 10: CB = total capacitance of one bus line in pF. tR and tF measured between 0.3 VDVDD and 0.7 VDVDD.
Note 11: fSCL must meet the minimum clock low time plus the rise/fall times.
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +4.75V to +5.25V, VDVDD = +2.7V to +5.5V, fSCL = 1.7MHz (33% duty cycle), fSAMPLE = 58.6ksps, VREF = +4.096V, external
reference applied to REF, REFADJ = AVDD, CREF = 10μF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
Figure 1. I2C Serial Interface Timing
tHD,STA
tHIGH
tR
tRCL
tF
tFCL
tHD,STA
S
Sr
A
SCL
SDA
tSU,STA
tSU,STO
tRCL1
tR
tF
tBUF
tLOW
tSU,DAT
tHD,DAT
PS
tSU,DAT
tHD,STA
S
Sr
A
SCL
SDA
tSU,STA
tLOW
P
S
HS-MODE
F/S-MODE
A. F/S-MODE I2C SERIAL INTERFACE TIMING
B. HS-MODE I2C SERIAL INTERFACE TIMING
tRDA
tFDA
PARAMETERS ARE MEASURED FROM 30% TO 70%.
Figure 2. Load Circuit
VOUT
VDD
IOL = 3mA
IOH = 0mA
400pF
DIGITAL
I/O
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