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參數(shù)資料
| 型號： | MAX11605EEE+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 23/23頁 |
| 文件大小： | 0K |
| 描述： | IC ADC SERIAL 8BIT 12CH 16-QSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 188k |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.75mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-QSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 12 個單端，單極；12 個單端，雙極；6 個差分，單極；6 個差分，雙極 |
minimize sampling errors with higher source imped-
ances, connect a 100pF capacitor from the analog
input to GND. This input capacitor forms an RC filter
with the source impedance limiting the analog input
bandwidth. For larger source impedances, use a buffer
amplifier to maintain analog input signal integrity.
When operating in internal clock mode, the T/H circuitry
enters its tracking mode on the ninth falling clock edge
of the address byte (see the
Slave Address section).
The T/H circuitry enters hold mode two internal clock
cycles later. A conversion or a series of conversions is
then internally clocked (eight clock cycles per conver-
sion) and the MAX11600–MAX11605 hold SCL low.
When operating in external clock mode, the T/H circuit-
ry enters track mode on the seventh falling edge of a
valid slave address byte. Hold mode is then entered on
the falling edge of the eighth clock cycle. The conver-
sion is performed during the next eight clock cycles.
The time required for the T/H circuitry to acquire an
input signal is a function of input capacitance. If the
analog input source impedance is high, the acquisition
time lengthens and more time must be allowed
between conversions. The acquisition time (tACQ) is the
minimum time needed for the signal to be acquired. It is
calculated by:
tACQ ≥ 6.25 (RSOURCE + RIN) CIN
where RSOURCE is the analog input source impedance,
RIN = 2.5k, and CIN = 18pF. tACQ is 1/fSCL for external
clock mode. For internal clock mode, the acquisition
time is two internal clock cycles. To select RSOURCE,
allow 625ns for tACQ in internal clock mode to account
for clock frequency variations.
MAX11600–MAX11605
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
_______________________________________________________________________________________
9
tHD.STA
tSU.DAT
tHIGH
tR
tF
tHD.DAT
tHD.STA
S
Sr
A
SCL
SDA
tSU.STA
tLOW
tBUF
tSU.STO
PS
tHD.STA
tSU.DAT
tHIGH
tFCL
tHD.DAT
tHD.STA
S
Sr
A
SCL
SDA
tSU.STA
tLOW
tBUF
tSU.STO
S
tRCL
tRCL1
HS MODE
F/S MODE
a) F/S-MODE I2C SERIAL-INTERFACE TIMING
b) HS-MODE I2C SERIAL-INTERFACE TIMING
tFDA
tRDA
t
tR
tF
Figure 1. I2C Serial-Interface Timing
VDD
IOL = 3mA
IOH = 0mA
VOUT
400pF
SDA
Figure 2. Load Circuit
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