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參數(shù)資料
| 型號： | MAX11605EEE+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 18/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC SERIAL 8BIT 12CH 16-QSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 188k |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.75mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-QSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 12 個單端，單極；12 個單端，雙極；6 個差分，單極；6 個差分，雙極 |
MAX11600–MAX11605
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 3.6V (MAX11601/MAX11603/MAX11605), VDD = 4.5V to 5.5V (MAX11600/MAX11602/MAX11604). External reference,
VREF = 2.048V (MAX11601/MAX11603/MAX11605), VREF = 4.096V (MAX11600/MAX11602/MAX11604). External clock, fSCL =
1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
MAX11601/MAX11603/MAX11605
2.7
3.6
Supply Voltage (Note 10)
VDD
MAX11600/MAX11602/MAX11604
4.5
5.5
V
Internal REF, external clock
350
650
fSAMPLE =
188ksps
External REF, external clock
250
External REF, external clock
110
fSAMPLE =
75ksps
External REF, internal clock
150
External REF, external clock
8
fSAMPLE =
10ksps
External REF, internal clock
10
External REF, external clock
2
fSAMPLE =
1ksps
External REF, internal clock
2.5
Supply Current
IDD
Power-down
1
10
A
Power-Supply Rejection Ratio
PSRR
(Note 11)
±0.25
±1
LSB/V
TIMING CHARACTERISTICS FOR 2-WIRE FAST MODE (Figures 1a and 2)
Serial-Clock Frequency
fSCL
400
kHz
Bus Free Time Between a STOP (P)
and a START (S) Condition
tBUF
1.3
s
Hold Time for START Condition
tHD.STA
0.6
s
Low Period of the SCL Clock
tLOW
1.3
s
High Period of the SCL Clock
tHIGH
0.6
s
Setup Time for a Repeated START
Condition (Sr)
tSU.STA
0.6
s
Data Hold Time
tHD.DAT
(Note 12)
0
150
ns
Data Setup Time
tSU.DAT
100
ns
Rise Time of Both SDA and SCL
Signals, Receiving
tR
(Note 13)
20 + 0.1CB
300
ns
Fall Time of SDA Transmitting
tF
(Note 13)
20 + 0.1CB
300
ns
Setup Time for STOP Condition
tSU.STO
0.6
s
Capacitive Load for Each Bus Line
CB
400
pF
Pulse Width of Spike Suppressed
tSP
50
ns
TIMING CHARACTERISTICS FOR 2-WIRE HIGH-SPEED MODE (Figures 1b and 2)
Serial-Clock Frequency
fSCLH
(Note 14)
1.7
MHz
Hold Time (Repeated) START
Condition
tHD.STA
160
ns
Low Period of the SCL Clock
tLOW
320
ns
High Period of the SCL Clock
tHIGH
120
ns
Setup Time for a Repeated START
Condition (Sr)
tSU.STA
160
ns
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