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參數(shù)資料
| 型號(hào)： | MAX115 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 2x4-Channel, Simultaneous-Sampling 12-Bit ADCs |
| 中文描述： | 2x4通道、同時(shí)采樣、12位ADC |
| 文件頁(yè)數(shù)： | 5/14頁(yè) |
| 文件大?。?/td> | 215K |
| 代理商： | MAX115 |
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M
2x4-Channel, Simultaneous-Sampling
12-Bit ADCs
_______________________________________________________________________________________
5
CONDITIONS
UNITS
MIN
TYP
MAX
2
4
6
8
390
218
152
116
SYMBOL
PARAMETER
TIMING CHARACTERISTICS (continued)
(See Figure 4, AV
DD
= +5V, AV
SS
= -5V, DV
DD
= +5V, AGND = DGND = 0, T
A
= T
MIN
to T
MAX
, Typical values are at T
A
= +25°C,
unless otherwise noted.)
Mode 1,
C
hannel 1
Mode 2,
C
hannel 2
Mode 3,
C
hannel 3
Mode 4,
C
hannel 4
Mode 1,
C
hannel 1
Mode 2,
C
hannel 2
Mode 3,
C
hannel 3
Mode 4,
C
hannel 4
μs
t
CONV
Exiting shutdown
ms
20
Startup Time
Note 1:
Note 2:
AV
DD
= +5V, AV
SS
= -5V, DV
DD
= +5V, V
REFIN
= 2.500V (external), V
IN
= ±5V (MAX115) or ±2.5V (MAX116).
Integral nonlinearity is the analog value’s deviation at any code from its theoretical value after the full-scale range and
offset have been calibrated.
CLK synchronized with
CONVST
.
f
IN
= 10.06kHz, V
IN
= ±5V (MAX115) or ±2.5V (MAX116).
First five harmonics.
All inputs except CH1A driven with ±5V (MAX115) or ±2.5V (MAX116) 10.06kHz signal, CH1A connected to AGND and digi-
tized.
AV
DD
= DV
DD
= +5V, AV
SS
= -5V, V
IN
= 0V (all channels).
Temperature drift is defined as the change in output voltage from +25°C to T
MIN
or T
MAX
. It is calculated as
TC = [
REFOUT/REFOUT] /
T.
See Figure 2.
Note 10:
Defined as the change in positive full scale caused by a ±5% variation in the nominal supply voltage. Tested with one input
at full scale and all others at AGND. V
REFIN
= +2.5V (internal).
Note 11:
Tested with all inputs connected to AGND. V
REFIN
= +2.5V (internal).
Note 12:
The data access time is defined as the time required for an output to cross +0.8V or +2.0V. It is measured using the circuit
of Figure 1. The measured number is then extrapolated back to determine the value with a 25pF load.
Note 13:
The bus relinquish time is derived from the measured time taken for the data outputs to change +0.5V when loaded with the
circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging and discharging the
120pF capacitor. The time given is the part’s true bus relinquish time, which is independent of the external bus loading capac-
itance.
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Conversion Time
ksps
Conversion Rate
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| MAX116EAX | 2x4-Channel, Simultaneous-Sampling 12-Bit ADCs |
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