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參數資料
| 型號： | MAX115 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 2x4-Channel, Simultaneous-Sampling 12-Bit ADCs |
| 中文描述： | 2x4通道、同時采樣、12位ADC |
| 文件頁數： | 10/14頁 |
| 文件大?。?/td> | 215K |
| 代理商： | MAX115 |
M
For multichannel conversions,
INT
goes low after the last
channel has been digitized.
To input data into the MAX115/MAX116, pull
CS
low,
program the bidirectional pins A0–A3 (Table 1), and
pulse
WR
low. Data is latched into the devices on the
WR
or
CS
rising edge. The ADC is now ready to convert.
Once programmed, the ADC continues operating in the
same mode until reprogrammed or until power is
removed. Figure 5 shows an example of programming a
four-channel conversion using Input Mux A.
Starting a Conversion
After programming the MAX115/MAX116 as outlined in
the
Programming Modes
section, pulse
CONVST
low to
initiate a conversion sequence. The analog inputs are
sampled at the
CONVST
rising edge. Do not start a
new conversion while the conversion is in progress.
Monitor the
INT
output. A falling edge indicates the end
of a conversion sequence.
Reading a Conversion
Digitized data from up to four channels is stored in
memory to be read out through the parallel interface.
After receiving an
INT
signal, the user can access up to
four conversion results by performing up to four read
operations.
With
CS
low, the conversion results from CH1_ are
accessed, and
INT
is reset high on the first
RD
falling
edge. On the
RD
rising edge, the internal address
pointer is advanced. If a single conversion is pro-
grammed, only one
RD
pulse is required. For multi-
channel conversions, up to four
RD
falling edges
sequentially access the data for channels 1 through 4.
For any number of channels converted, the address
pointer is reset to CH1_ after four
RD
pulses. The
address pointer also resets after receiving a
CNVST
pulse. Do not perform a read operation during conver-
sion; it will corrupt the conversion’s accuracy.
__________Applications Information
Clock
The MAX115/MAX116 have an internal 10MHz (typ)
clock, which is activated by connecting CLK to DV
DD
(internal clock startup time is 165μs typ). The CLK input
also accepts an external clock with duty cycle between
30% and 70%.
2x4-Channel, Simultaneous-Sampling
12-Bit ADCs
10
______________________________________________________________________________________
X = Don’t care
Table 1. Modes of Operation
TO DAC
REFIN
10k
0.1
μ
F
4.7
μ
F
A
V
= 1
2.5V
REFOUT
7
6
(2.5V)
(2.5V)
MAX115
MAX116
Figure 6. Internal Reference
Input Mux A/Single-Channel Conversion (default at power-up)
Input Mux A/Two-Channel Conversion
Power-Down
—
X
X
X
1
Input Mux B/Four-Channel Conversion
8
1
1
1
0
Input Mux B/Three-Channel Conversion
6
0
1
1
0
Input Mux B/Two-Channel Conversion
4
1
0
1
0
Input Mux B/Single-Channel Conversion
2
0
0
1
0
Input Mux A/Four-Channel Conversion
Input Mux A/Three-Channel Conversion
MODE
8
6
4
2
CONVERSION
TIME (μs)
1
0
1
0
A0
1
0
0
1
0
0
0
0
0
0
0
0
A1
A2
A3
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