參數(shù)資料
型號(hào)： MAX1126EGK
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： ADC
英文描述： Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs
中文描述： 4-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, QCC68
封裝： 10 X 10 MM, 0.90 MM HEIGHT, MO-220, QFN-68
文件頁(yè)數(shù)： 6/25頁(yè)
文件大?。?/td> 790K
代理商： MAX1126EGK
M
Quad, 12-Bit, 40Msps, 1.8V ADC with
S erial LV DS Outputs
6
_______________________________________________________________________________________
Note 1:
Specifications at T
A
≥
+25°C are guaranteed by production testing. Specifications at T
A
< +25°C are guaranteed by design
and characterization and not subject to production testing.
Note 2:
See definition in the
Parameter Definitions
section.
Note 3:
The MAX1126 internally sets the common-mode voltage to 0.6V (typ) (see Figure 1). The common-mode voltage can be
overdriven to between 0.55V and 0.85V.
Note 4:
Limited by MAX1127EVKIT input circuitry.
Note 5:
Connect
INTREF
to GND directly to enable internal reference mode. Connect
INTREF
to AV
DD
directly to disable the internal
bandgap reference and enable external reference mode.
Note 6:
Data valid to CLKOUT rise/fall timing is measured from 50% of data output level to 50% of clock output level.
Note 7:
Guaranteed by design and characterization. Not subject to production testing.
Note 8:
Sample CLK Rise to FRAME RISE timing is measured from 50% of sample clock input level to 50% of FRAME output level.
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= 1.8V, OV
DD
= 1.8V, CV
DD
= 1.8V, GND = 0, external V
REFIO
= 1.24V,
INTREF
= AV
DD
, C
REFIO
to GND = 0.1μF,
f
CLK
= 40MHz (50% duty cycle), DT = 0, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25
°
C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CHANNEL-TO-CHANNEL MATCHING
Crosstalk
Gain Matching
Phase Matching
(Note 2)
f
IN
= 19.3MHz (Note 2)
f
IN
= 19.3.MHz (Note 2)
-90
±0.1
±1
dB
dB
Degrees
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相關(guān)代理商/技術(shù)參數(shù)
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