參數(shù)資料
型號(hào): MAX1126EGK
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: ADC
英文描述: Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs
中文描述: 4-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, QCC68
封裝: 10 X 10 MM, 0.90 MM HEIGHT, MO-220, QFN-68
文件頁(yè)數(shù): 3/25頁(yè)
文件大?。?/td> 790K
代理商: MAX1126EGK
M
Quad, 12-Bit, 40Msps, 1.8V ADC with
S erial LV DS Outputs
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= 1.8V, OV
DD
= 1.8V, CV
DD
= 1.8V, GND = 0, external V
REFIO
= 1.24V,
INTREF
= AV
DD
, C
REFIO
to GND = 0.1μF,
f
CLK
= 40MHz (50% duty cycle), DT = 0, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25
°
C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
93.7
89
-91.5
-88.7
MAX
UNITS
f
IN
= 5.3MHz at -0.5dBFS
f
IN
= 19.3MHz at -0.5dBFS, T
A
+25°C
f
IN
= 5.3MHz at -0.5dBFS
f
IN
= 19.3MHz at -0.5dBFS, T
A
+25°C
f
1
= 12.40125MHz at -6.5dBFS,
f
2
= 13.60125MHz at -6.5dBFS ( N ote 2)
Spurious-Free Dynamic Range
(Note 2)
SFDR
77.3
dBc
Total H ar m oni c D stor i on ( N ote 2)
THD
-76.3
dBc
Inter m od ul ati on D stor i on
IMD
87.0
dBc
Third-Order Intermodulation
IM3
f
1
= 12.40125MHz at -6.5dBFS,
f
2
= 13.60125MHz at -6.5dBFS ( N ote 2)
(Note 2)
(Note 2)
Input at -20dBFS (Notes 2 and 4)
Input at -0.5dBFS (Notes 2 and 4)
IN_P = IN_N
89.3
dBc
Aperture J itter
Aperture Delay
Small-Signal Bandwidth
Full-Power Bandwidth
Output Noise
t
AJ
t
AD
SSBW
LSBW
<0.4
1
100
100
0.35
ps
RMS
ns
MHz
MHz
LSB
RMS
Clock
cycles
Overdrive Recovery Time
t
OR
R
S
= 25
, C
S
= 50pF
1
INTERNAL REFERENCE (
INTREF
= GND, bypass REFIO to GND with 0.1μF)
INTREF
Internal Reference Mode
Enable Voltage
(Note 5)
0.1
V
INTREF
Low-Leakage Current
REFIO Output Voltage
200
1.24
μA
V
V
REFIO
1.18
1.30
Reference Temperature
Coefficient
TC
REFIO
100
ppm/°C
EXTERNAL REFERENCE (
INTREF
= AV
DD
)
INTREF
External Reference Mode
Enable Voltage
(Note 5)
AV
DD
-
0.1V
V
INTREF
High-Leakage Current
REFIO Input Voltage Range
REFIO Input Current
CLOCK INPUT (CLK)
200
1.24
<1
μA
V
μA
I
REFIO
Input High Voltage
V
CLKH
0.8 x
CV
DD
V
Input Low Voltage
V
CLKL
0.2 x
CV
DD
V
Clock Duty Cycle
Clock Duty-Cycle Tolerance
50
±30
%
%
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