參數(shù)資料
型號: MAX11211EEE+T
廠商: Maxim Integrated Products
文件頁數(shù): 13/27頁
文件大小: 0K
描述: ADC 18BIT DELTA-SIGMA 16-QSOP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
位數(shù): 18
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 667mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-QSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: *
20
Maxim Integrated
18-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
MAX11209/MAX11211
CTRL2: Control 2 Register
The byte-wide CTRL2 register is a bidirectional read/write register. The byte written to the CTRL2 register controls the
direction and values of the digital I/O ports.
DIR[4:1]: The direction bits configure the direction of the DIO bit. When a DIR bit is set to 0, the associated DIO bit
is configured as an input and the value returned by a read of the DIO bit is the value being driven on the associated
GPIO. When a DIR bit is set to 1, the associated DIO bit is configured as an output and the GPIO port is driven to a
logic value of the associated DIO bit.
DIO[4:1]: The data input/output bits are bits associated with the GPIO ports. When a DIO is configured as an input,
the value read from the DIO bit is the logic value being driven at the GPIO port. When the direction is configured as an
output, the GPIO port is driven to a logic value associated with the DIO bit.
CTRL3: Control 3 Register
The byte-wide CTRL3 register is a bidirectional read/write register. The CTRL3 register controls the operation and
calibration of the device.
DGAIN[2:0] (MAX11209 only): The digital gain bits control the input referred gain. With a gain of 1, the input range is
0 to VREF (unipolar) or ±VREF (bipolar). As the gain in increased by 2x, the input range is reduced to 0 to VREF/gain
or ±VREF/gain. Digital gain is applied to the final offset and gain-calibrated digital data. The DGAIN[2:0] bits decode
to digital gains as follows:
000 = 1
100 = 16
001 = 2
101 = 32
010 = 4
110 = 64
011 = 8
111 = 128
NOSYSG: The no-system gain bit, NOSYSG, controls the system gain calibration coefficient. A 1 in this bit location disables
the use of the system gain value when computing the final offset and gain corrected data value. A 0 in this location enables
the use of the system gain value when computing the final offset and gain corrected data value.
NOSYSO: The no system offset bit, NOSYSO, controls the system offset calibration coefficient. A 1 in this location disables
the use of the system offset value when computing the final offset and gain corrected data value. A 0 in this location enables
the use of the system offset value when computing the final offset and gain corrected data value.
NOSCG: The no self-calibration gain bit, NOSCG, controls the self-calibration gain calibration coefficient. A 1 in this location
disables the use of the self-calibration gain value when computing the final offset and gain corrected data value. A 0 in this
location enables the use of the self-calibration gain value when computing the final offset and gain corrected data value.
NOSCO: The no self-calibration offset bit, NOSCO, controls the use of the self-calibration offset calibration coefficient. A 1 in
this location disables the use of the self-calibration offset value when computing the final offset and gain corrected data value.
A 0 in this location enables the use of the self-calibration offset value when computing the final offset and gain corrected data
value.
Table 13. CTRL2 Register (Read/Write)
Table 14. CTRL3 Register (Read/Write)
*These DGAIN_ bits are don’t-care bits for the MAX11209.
BIT
B7
B6
B5
B4
B3
B2
B1
B0
BIT NAME
DIR4
DIR3
DIR2
DIR1
DIO4
DIO3
DIO2
DIO1
DEFAULT
0
1
BIT
B7
B6
B5
B4
B3
B2
B1
BIT NAME
DGAIN2*
DGAIN1*
DGAIN0*
NOSYSG
NOSYSO
NOSCG
NOSCO
RESERVED
DEFAULT
0
1
0
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