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參數(shù)資料
| 型號： | MAX1118EKA+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 13/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8-BIT 100KSPS SOT23-8 |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 680µW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-8 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸入數(shù)目和類型： | 2 個單端，單極 |
| 產(chǎn)品目錄頁面： | 1395 (CN2011-ZH PDF) |
| 其它名稱： | MAX1118EKA+TDKR |
MAX1117/MAX1118/MAX1119
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
8
_______________________________________________________________________________________
VDD
I/O
SCK (SK)
MISO (SI)
GND
DOUT
SCLK
CNVST
GND
VDD
0.1
μF
1
μF
CH0
REF*
* MAX1118 ONLY
1
μF
ANALOG
INPUTS
MAX1117
MAX1118
MAX1119
CPU
VDD
CH1
Figure 3. Typical Operating Circuit
GND
CHOLD
CAPACITIVE DAC
COMPARATOR
16pF
RIN
6.5k
Ω
AUTOZERO
RAIL
TRACK
HOLD
CH0
CH1
Figure 4. Equivalent Input Circuit
Detailed Description
The MAX1117/MAX1118/MAX1119 ADCs use a suc-
cessive-approximation conversion technique and input
T/H circuitry to convert an analog signal to an 8-bit digi-
tal output. The SPI/QSPI/MICROWIRE compatible inter-
face directly connects to microprocessors (Ps) without
additional circuity (Figure 3).
Track/Hold
The input architecture of the ADC is illustrated in Figure
4’s equivalent-input circuit and is composed of the T/H,
the input multiplexer, the input comparator, the
switched capacitor DAC, and the auto-zero rail.
The acquisition interval begins with the falling edge of
CNVST. During the acquisition interval, the analog
inputs (CH0, CH1) are connected to the holding capac-
itor (CHOLD). Once the acquisition has completed, the
T/H switch opens and CHOLD is connected to GND,
retaining the charge on CHOLD as a sample of the sig-
nal at the analog input.
Sufficiently low source impedance is required to ensure
an accurate sample. A source impedance <1.5k
Ω is
recommended for accurate sample settling. A 100pF
capacitor at the ADC inputs will also improve the accu-
racy of an input sample.
Conversion Process
The MAX1117/MAX1118/MAX1119 conversion process
is internally timed. The total acquisition and conversion
process takes <7.5s. Once an input sample has been
acquired, the comparator’s negative input is then con-
VDD
3k
Ω
CLOAD
GND
DOUT
CLOAD
GND
3k
Ω
DOUT
a) VOL TO VOH
b) HIGH-Z to VOL AND VOH to VOL
VDD
3k
Ω
CLOAD
GND
DOUT
CLOAD
GND
3k
Ω
DOUT
a) VOH TO HIGH-Z
b) VOL TO HIGH-Z
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disable Time
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相關(guān)代理商/技術(shù)參數(shù) |
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| MAX1119 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs |
| MAX11190ETE+ | 制造商:Maxim Integrated Products 功能描述:DUAL, 2.2V TO 3.6V, 12-BIT, 3MSPS SAR ADC IN TINY TQFN PACKA - Rail/Tube |
| MAX11190ETE+T | 制造商:Maxim Integrated Products 功能描述:DUAL, 2.2V TO 3.6V, 12-BIT, 3MSPS SAR ADC IN TINY TQFN PACKA - Tape and Reel |
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