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參數(shù)資料
| 型號： | MAX1111MJE |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | +2.7V, Low-Power, Multichannel, Serial 8-Bit ADCs |
| 中文描述： | 4-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP16 |
| 封裝： | CERAMIC, DIP-16 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 284K |
| 代理商： | MAX1111MJE |
M
+2.7V, Low-Power, Multic hannel,
S erial 8-Bit ADCs
_______________________________________________________________________________________
5
ns
100
t
CSS
t
CSH
t
CH
t
CL
t
SSTRB
Figure 1, external clock mode only,
C
LOAD
= 100pF
ns
CS
to SCLK Rise Setup
240
Figure 1, C
LOAD
= 100pF
Figure 2, C
LOAD
= 100pF
ns
20
200
ns
0
CONDITIONS
CS
to SCLK Rise Hold
240
t
DV
t
TR
CS
Fall to Output Enable
ns
240
CS
Rise to Output Disable
t
SDV
CS
Fall to SSTRB Output Enable
(Note 6)
Figure 2, external clock mode only,
C
LOAD
= 100pF
ns
240
t
STR
CS
Rise to SSTRB Output
Disable (Note 6)
Figure 11, internal clock mode only
ns
0
t
SCK
SSTRB Rise to SCLK Rise
(Note 6)
ns
200
SCLK Pulse Width High
ns
200
SCLK Pulse Width Low
C
LOAD
= 100pF
ns
240
SCLK Fall to SSTRB
ns
0
t
DH
DIN to SCLK Hold
μs
1
t
ACQ
t
DS
Track/Hold Acquisition Time
ns
100
DIN to SCLK Setup
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
TIMING CHARACTERISTICS
(Figures 8 and 9)
(V
DD
= +2.7V to +5.5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Measured as
|
V
FS
(2.7V) - V
FS
(3.6V)
|
.
Note 11:
1μF at REFOUT; internal reference settling to 0.5LSB.
Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is calibrated.
See Typical Operating Characteristics.
V
REFIN
= 2.048V, offset nulled.
On-channel grounded; sine wave applied to all off-channels.
Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Guaranteed by design. Not subject to production testing.
Common-mode range for the analog inputs is from AGND to V
DD
.
External load should not change during the conversion for specified accuracy.
External reference at 2.048V, full-scale input, 500kHz external clock.
ns
20
240
t
DO
SCLK Fall to Output Data Valid
Figure 1,
C
LOAD
= 100pF
MAX111_C/E
MAX111_M
External reference
20
Internal reference (Note 11)
μs
12
t
WAKE
Wake-Up Time
ms
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