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參數(shù)資料
| 型號： | MAX110 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Low-Cost, 2-Channel, 4-Bit Serial ADCs(±5V，2通道，±14位串行模數(shù)轉(zhuǎn)換器) |
| 中文描述： | 低成本、2通道、±14位串行ADC |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 286K |
| 代理商： | MAX110 |
M
Low-Cost, 2-Channel, ±14-Bit S erial ADCs
6
_______________________________________________________________________________________
Note 10:
Timing specifications are sample tested at +25°C to ensure compliance. All input control signals are specified
with t
r
= t
f
= 5ns (10% to 90% of +5V) and timed from a +1.6V voltage level.
Note 1:
These specifications apply after auto-null and gain calibration. Performance at power-supply tolerance limits is guaranteed
by power-supply rejection tests. Tests are performed at V
DD
= 5V and V
SS
= -5V (MAX110).
Note 2:
32,768 LSBs cover an input voltage range of ±V
REF
(15 bits). An additional bit (OFL) is set for V
IN
> V
REF
.
Note 3:
Guaranteed by design. Not subject to production testing.
Note 4:
DNL is less than ±2 counts (LSBs) out of 2
15
counts (±14 bits). The major source of DNL is noise, and this can be further
improved by averaging.
Note 5:
See 3-Step Calibrationsection in text.
Note 6:
V
REF
= (V
REF+
- V
REF-
), V
IN
= (V
IN1+
- V
IN1-
) or (V
IN2+
- V
IN2-
). The voltage is interpreted as negative when the voltage at
the negative input terminal exceeds the voltage at the positive input terminal.
Note 7:
Conversion time is set by control bits CONV1–CONV4.
Note 8:
Tested at clock frequency of 1MHz with the divide-by-2 mode (i.e. oversampling clock of 500kHz). See Typical Operating
Characteristics section for the effect of other clock frequencies. Also read the Clock Frequency section.
Note 9:
This current depends strongly on C
XCLK
(see Applications Informationsection).
TIMING CHARACTERISTICS
(see Figure 6)
(V
DD
= 5V, V
SS
= -5V (MAX110), T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
MHz
1.1
3.0
MAX11_ BM
RC Oscillator Frequency
1.3
2.8
MAX11_ _C/E
2.0
T
A
= +25°C
PARAMETER
SYMBOL
MIN
60
80
100
TYP
MAX
UNITS
80
100
60
CS
to SCLK Hold Time
(Note 10)
t
CSH
0
ns
DIN to SCLK Setup Time
(Note 10)
t
DS
ns
DIN to SCLK Hold Time
(Note 10)
t
DH
0
ns
100
120
160
0
0
0
0
0
0
CS
to SCLK Setup Time
(Note 10)
t
CSS
ns
SCLK, XCLK Pulse Width
(Note 10)
t
CK
ns
35
80
100
120
100
120
140
80
120
Data Access Time
(Note 10)
t
DA
ns
60
SCLK to DOUT Valid
Delay (Note 10)
t
DO
ns
35
Bus Relinquish Time
(Note 10)
t
DH
ns
MAX11_ BM
T
A
= +25°C
MAX11_ _C/E
T
A
= +25°C
MAX11_ BM
MAX11_ _C/E
CONDITIONS
MAX11_ _C/E
MAX11_ BM
MAX11_ _C/E
MAX11_ BM
T
A
= +25°C
T
A
= +25°C
C
LOAD
= 50pF
T
A
= +25°C
MAX11_ _C/E
MAX11_ BM
C
LOAD
= 50pF
T
A
= +25°C
MAX11_ _C/E/M
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