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參數(shù)資料
| 型號： | MAX11060GUU+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 31/35頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT DELTA SIGMA 38TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 3.07M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 功率耗散（最大）： | 1.1W |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 106°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 38-TFSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 38-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個單端，雙極；4 個差分，雙極 |
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MAX11040K/MAX11060
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
5
Maxim Integrated
Note 1: Devices are production tested at +105°C. Specifications to -40°C are guaranteed by design.
Note 2: Tested at VAVDD = VDVDD = +3.0V.
Note 3: Integral nonlinearity is the deviation of the analog value at any code from its ideal value after the offset and gain errors are
removed.
Note 4: Offset nulled.
Note 5: Offset and gain drift defined as change in offset and gain error vs. full scale.
Note 6: Noise measured with AIN_+ = AIN_- = AGND.
Note 7: Relative accuracy is defined as the difference between the actual RMS amplitude and the ideal RMS amplitude of a 62.5Hz
sine wave, measured over one cycle at a 16ksps data rate, expressed as a fraction of the ideal RMS amplitude. The rela-
tive accuracy specification refers to the maximum error expected over 1 million measurements. Calculated from SNR. Not
production tested.
Note 8: Latency is a function of the sampling rate and XIN clock.
Note 9: Voltage levels below the positive fault threshold and above the negative fault threshold, relative to AGND on each individ-
ual AIN_+ and AIN_- input, do not trigger the analog input protection circuitry.
Note 10: Test performed using RXD MP35.
Note 11: All digital inputs at DGND or DVDD.
Note 12: SYNC is captured by the subsequent XIN clock if this specification is violated.
Note 13: Delay from DVDD exceeds 2.0V until digital interface is operational.
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +3.0V to +3.6V, VDVDD = +2.7V to VAVDD, fXIN CLOCK = 24.576MHz, fOUT = 16ksps, VREFIO = +2.5V (external), CREFIO =
CREF0 = CREF1 = CREF2 = CREF3 = 1μF to AGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CLOAD = 30pF
1.5
10
16
SCLK Rise to DOUT Valid
tDOT
CLOAD = 100pF
< 16
ns
CS Fall to DOUT Enable
tDOE
CLOAD = 30pF
0.3
20
ns
CS Rise to DOUT Disable
tDOD
CLOAD = 30pF
0.7
16
ns
CS Pulse Width
tCSW
16
ns
CASCIN-to-SCLK Rise Setup
tSC
16
ns
SCLK Rise to CASCOUT Valid
tCOT
CLOAD = 100pF
20
ns
SYNC Pulse Width
tSYN
2
XIN
Clock
Cycles
XIN Clock Pulse Width
tXPW
16
ns
DRDYIN to DRDYOUT
tDRDY
CLOAD = 30pF
20
ns
XIN Clock to DRDYOUT Delay
tXDRDY
DRDYIN = DGND
40
ns
XIN Clock Period
tXP
40
ns
XIN Clock to SYNC Setup
tSS
(Note 12)
16
ns
SYNC to XIN Clock Hold
tHS
(Note 12)
5
ns
XIN-to-CLKOUT Delay
tXCD
40
ns
Power-On Reset Delay
(Note 13)
< 1
ms
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