參數(shù)資料
型號： MAX11060GUU+T
廠商： Maxim Integrated Products
文件頁數(shù)： 14/35頁
文件大?。?/td> 0K
描述： IC ADC 16BIT DELTA SIGMA 38TSSOP
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 2,500
位數(shù)： 16
采樣率（每秒）： 3.07M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 1.1W
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 106°C
安裝類型： 表面貼裝
封裝/外殼： 38-TFSOP（0.173"，4.40mm 寬）
供應商設備封裝： 38-TSSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 8 個單端，雙極；4 個差分，雙極
MAX11040K/MAX11060
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
21
Maxim Integrated
Data Rate Control Register
The Data Rate Control register controls the output data
period, which corresponds to the output data rate of
the ADC. The data period is controlled by both a
coarse (FSAMPC[2:0]) and a fine (FSAMPF[10:0])
adjustment (see Table 8).
The final data rate is derived by dividing the XIN clock
frequency by a divider value. The divider value is a
function of FSAMPC[2:0] and FSAMPF[10:0]:
Data Rate = fXINCLOCK/Divider
Divider = Coarse Cycle Factor x 384 + Fine Cycle
Factor x FSAMPF[10:0]
Note: Fractional results for the divider are rounded
down to the nearest integer. Coarse cycle factor and
fine cycle factor come from Table 8. The effect of
FSAMPF[10:0] in the formula has limitations as noted in
the table.
Examples of output data rate vs. FSAMPC[2:0] and
FSAMPF[10:0] are shown in Table 9. Table 10 shows
typical device performance for various data rate settings.
CS
DIN
SCLK
DOUT
CASCOUT0
(CASCIN0 = 0)
DRDYOUT0
(DRDYIN0 = 0)
DRDYOUT1
CASCOUT1
DEVICE 0 DATA READY
DEVICE 0 AND DEVICE 1 DATA READY
24 CYCLES
CHANNEL 0
DEVICE 0
CHANNEL 1
DEVICE 0
CHANNEL 2
DEVICE 0
CHANNEL 3
DEVICE 0
CHANNEL 0
DEVICE 1
CHANNEL 1
DEVICE 1
CHANNEL 2
DEVICE 1
CHANNEL 3
DEVICE 1
24 CYCLES
DEVICE 1 TAKES OVER SPI BUS
Figure 11. 192-Bit Data Read Operation Diagram for Two Cascaded Devices
Table 7. Data Register (MAX11060) (continued)
BIT
NAME
DESCRIPTION
[31:29]
000
—
[28:26]
IC[2:0]
Device address tag. IC[2:0] starts with 000 for the device nearest the master.
[25:24]
10
Channel 2 address tag = 10
[23:8]
CH3DATA[15:0]
Channel 3 16-bit conversion result (two’s complement)
[7:5]
000
—
[4:2]
IC[2:0]
Device address tag. IC[2:0] starts with 000 for the device nearest the master.
[1:0]
11
Channel 3 address tag = 11
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