參數(shù)資料
型號: MAX11040KGUU+T
廠商: Maxim Integrated Products
文件頁數(shù): 3/35頁
文件大?。?/td> 0K
描述: IC ADC 24BIT 4CH 38TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
位數(shù): 24
采樣率(每秒): 3.07M
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 4
功率耗散(最大): 1.1W
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 38-TFSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 38-TSSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 4 個差分,雙極
MAX11040K/MAX11060
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
11
Maxim Integrated
Pin Description (continued)
PIN
NAME
FUNCTION
22
DRDYOUT
Active-Low Data Ready Output. When DRDYIN = 0, DRDYOUT outputs a logic-low to indicate the
availability of a new conversion result. DRDYOUT transitions high at the next CS falling edge or when
DRDYIN = 1. See the Multiple Device Connection section.
23
DRDYIN
Active-Low Data Ready Input. A logic-high at DRDYIN causes DRDYOUT to output a logic-high. When
DRDYIN = 0, DRDYOUT outputs a logic-low when a new conversion result is available. See the Multiple
Device Connection section. Connect DRDYIN to DGND when not daisy chaining multiple devices.
24
SYNC
Sampling Synchronization Input. The falling edge of SYNC aligns sampling and output data so that
multiple devices sample simultaneously. Synchronize multiple devices running from independent crystals
by connecting DRDYOUT of the last device in the chain to the SYNC inputs of all devices in the chain.
Connect SYNC to DGND for single device operation. See the Multiple Device Connection section.
25
XOUT
Crystal Oscillator Output. Connect a 24.576MHz external crystal or resonator between XIN and XOUT
when using the internal oscillator. Leave XOUT unconnected when driving with an external frequency. See
the Crystal Oscillator section.
26
XIN
Crystal Oscillator/Clock Input. Connect a 24.576MHz external crystal or resonator between XIN and XOUT
when using the internal oscillator or drive XIN with an external clock and leave XOUT unconnected. See
the Crystal Oscillator section.
30
AVDD
Positive Analog Supply Voltage. Bypass to AGND with a 1μF capacitor in parallel with a 0.01μF capacitor
as close as possible to the device.
32
REF3
ADC3 Buffered Reference Voltage. Bypass with a 1μF capacitor to AGND.
33
AIN3+
Positive Analog Input Channel 3
34
AIN3-
Negative Analog Input Channel 3
36
REF2
ADC2 Buffered Reference Voltage. Bypass with a 1μF capacitor to AGND.
37
AIN2+
Positive Analog Input Channel 2
38
AIN2-
Negative Analog Input Channel 2
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