參數(shù)資料
型號： MAX11040KGUU+T
廠商： Maxim Integrated Products
文件頁數(shù)： 25/35頁
文件大?。?/td> 0K
描述： IC ADC 24BIT 4CH 38TSSOP
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 2,500
位數(shù)： 24
采樣率（每秒）： 3.07M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 1.1W
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 38-TFSOP（0.173"，4.40mm 寬）
供應商設備封裝： 38-TSSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個差分，雙極
MAX11040K/MAX11060
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
31
Maxim Integrated
DISCONTINUITY DUE TO SYNC EVENT
DRDYOUT
SYNC
MEASURE
tDRYOUT_TO_SYNC
AIN_
RECONSTRUCTED
DIGITAL OUTPUT
PAUSE FOR
tDRYOUT_TO_SYNC
NOTE: THE LATENCY IS NOT TO SCALE.
tDRYOUT_TO_SYNC
1
2
3
4
2
3
4
5
6
1
2
3
4
5
6
tS
Figure 19. Example of Discontinuity in Reconstructed Digital Output Due to SYNC Falling Edge with a Large DRDYOUT-to-SYNC Delay
Signal Distortion at
SYNC Falling Edges
Each SYNC falling edge causes a disruption in the digi-
tal filter timing proportional to the delay from the previ-
ous falling edge of DRDYOUT to the falling edge of
SYNC. Any analysis of the output data that assumes a
uniform sampling period sees an error proportional to
that delay, with a maximum value determined by the
maximum derivative of the analog input. Figure 19
shows the effect of this discontinuity at output sample 5.
Assuming a 60Hz ±2.2V sine wave, the maximum pos-
sible error on any given sample caused by a SYNC
falling edge is:
VERROR_MAX = 2.2V x 2π x 60Hz x tDRDYOUT_TO_SYNC
= 0.83μV/ns x tDRDYOUT_TO_SYNC
The delay from DRDYOUT to SYNC is quantized to
within one cycle of the 24.576MHz clock. SYNC pulses
that are asynchronous to DRDYOUT may cause large
errors. To eliminate this error, use a single clock source
for all devices and avoid disrupting the output data tim-
ing with SYNC pulses while making high-precision
measurements. Alternately, minimize the delay from
DRDYOUT to SYNC to minimize the error.
Example:
Assume fAIN_ = 60Hz, fS = 16ksps, and eight total
devices in the chain.
Device 1 has the longest tDRDYOUT_TO_SYNC delay,
therefore the worst-case SYNC error.
If device 1 has the fastest XIN clock in the chain, and
device 2 has the slowest XIN clock in the chain, and
they differ by 0.1%, device 1 completes its conversion
as much as 0.1% earlier than device 2. Hence, the
delay of device 2 is:
0.1% x (1/16kHz ) = 62.5ns
The signal then propagates down the chain at a time
delay of nominally 20ns for each device.
The total delay back to the SYNC falling edge after
going through six additional delays is:
tDELAY = 62.5ns + 6 x 20ns = 182.5ns
Maximum % Error = 2
π x fIN x tDRDYOUT_TO_SYNC x
100% = 2 x π x 60Hz x 182.5ns x 100% = 0.007%
The above error is relative to the signal level, not to the
full scale of the data converter.
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