參數(shù)資料
型號： MAX109
廠商： Maxim Integrated Products, Inc.
元件分類： 運動控制電子
英文描述： 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs
中文描述： 8位、2.2Gsps ADC，提供采樣/保持放大器和1:4解復(fù)用LVDS輸出
文件頁數(shù)： 22/29頁
文件大小： 451K
代理商： MAX109
M
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier
and 1:4 Demultiplexed LVDS Outputs
22
______________________________________________________________________________________
ble input drive requirements. Each clock input is termi-
nated with an on-chip, laser-trimmed 50
resistor to
CLKCOM (clock-termination return). The CLKCOM ter-
mination voltage can be connected anywhere between
ground and -2V for compatibility with standard-ECL drive
levels. The clock inputs are internally buffered with a pre-
amplifier to ensure proper operation of the data convert-
er, even with small-amplitude sine-wave sources. The
MAX109 was designed for single-ended, low-phase
noise sine-wave clock signals with as little as 100mV
amplitude (-10dBm), thereby eliminating the need for an
external ECL clock buffer and its added jitter.
Single-Ended Clock Inputs (Sine-Wave Drive)
Excellent performance is obtained by AC- or DC-cou-
pling a low-phase-noise sine-wave source into a single
clock input (Figure 13a, Table 6). For proper DC bal-
ance, the undriven clock input should be externally
Table 4. Digital Output Codes Corresponding to a DC-Coupled
Single-Ended Analog Input
IN-PHASE/TRUE INPUT
(INP)
INVERTED/COMPLEMENTARY
INPUT (INN)
OUT-OF-RANGE BIT
(DORP/DORN)
OUTPUT CODE
250mV
0
0
0
0
0
0
1
0
0
0
0
1
11111111 (full scale)
11111111
10000000 toggles 01111111
00000001
00000000 (zero scale)
00000000 (out of range)
250mV - 1 LSB
0
-250mV + 1 LSB
-250mV
<-250mV
Table 5. Digital Output Codes Corresponding to a DC-Coupled Differential Analog Input
IN-PHASE/TRUE INPUT
(INP)
INVERTED/COMPLEMENTARY
INPUT (INN)
OUT-OF-RANGE BIT
(DORP/DORN)
OUTPUT CODE
125mV
-125mV
1
0
0
0
0
1
11111111 (full scale)
11111111
10000000 toggles 01111111
00000001
00000000 (zero scale)
00000000 (out of range)
125mV - 0.5 LSB
0
-125mV + 0.5 LSB
-125mV
<-125mV
-125mV + 0.5 LSB
0
125mV - 0.5 LSB
125mV
>+125mV
Table 6. Driving Options for DC-Coupled Clock
CLOCK DRIVE
Single-ended sine wave
Differential sine wave
Single-ended ECL
Differential ECL
CLKP
CLKN
CLKCOM
GNDI
GNDI
-2V
-2V
REFERENCE
Figure 13a
Figure 13b
Figure 13c
Figure 13d
-10dBm to +15dBm
-10dBm to +10dBm
ECL drive
ECL drive
Externally terminated to GNDI with 50
-10dBm to +10dBm
-1.3V
ECL
drive
Table 7. Demultiplexer and Reset Operations
SIGNAL/PIN NAME
CLKP/CLKN
DCOP/DCON
RSTINP/RSTINN
RSTOUTP/RSTOUTN
TYPE
FUNCTIONAL DESCRIPTION
Sampling clock inputs
LVDS outputs
LVDS inputs
LVDS outputs
Master ADC timing signal. The ADC samples on the rising edge of CLKP.
Data clock output (LVDS). Output data changes on the rising edge of DCOP.
D em ul i p exer r eset i np ut si g nal s. Resets the i nter nal d em ul i p exer w hen asser ed
Reset outputs for synchronizing the resets of multiple external devices.
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