參數(shù)資料
型號(hào)： MAX109
廠商： Maxim Integrated Products, Inc.
元件分類(lèi)： 運(yùn)動(dòng)控制電子
英文描述： 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs
中文描述： 8位、2.2Gsps ADC，提供采樣/保持放大器和1:4解復(fù)用LVDS輸出
文件頁(yè)數(shù)： 13/29頁(yè)
文件大?。?/td> 451K
代理商： MAX109
M
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier
and 1:4 Demultiplexed LVDS Outputs
______________________________________________________________________________________
13
PIN
NAME
Pin Description (continued)
PIN
A14
NAME
CLKP
FUNCTION
True/Positive Sampling Clock Input. Positive terminal for differential input configuration.
A16
CLKN
Complementary/Negative Sampling Clock Input. Negative terminal for differential input
configuration.
A13, A15, A17,
B14, B15, B16,
C14, C15, C16,
D14, D15, D16
CLKCOM
50
Clock Termination Return
B20
SAMPADJ
Sampling Point Adjustment Input. Allows the user to adjust the sampling event by applying a
voltage between 0 to 2.5V to this input.
B19
DELGATE1
Timing Delay Adjustment. Coarse (MSB) adjustment for the timing between T/H amplifier and
quantizer.
C19
DELGATE0
Timing Delay Adjustment. Coarse (LSB) adjustment for the timing between T/H amplifier and
quantizer.
Y20
REFIN
Reference Voltage Input. For applications requiring improved gain performance and reference-
voltage adjustability, allows the user to utilize the REFIN input by applying a more accurate and
adjustable reference source. This input accepts an input-voltage range of 2.5V ±10%.
Y19
REFOUT
Internal Reference Output. Connect to REFIN, if using the internal 2.5V bandgap reference.
V18, W18, Y18
GNDR
Bandgap Reference Ground. Ground connection for the internal bandgap reference and its
related circuitry.
M20
INP
True/Positive Analog Input Terminal. For single-ended signals, apply signal to INP and reverse-
terminate INN to GNDI with a 50
resistor.
K20
INN
C om p em entar y/N eg ati ve Anal og Inp ut Ter m nal For si ng ed end ed si g nal s, r ever se- er m nate IN N to
GN D w h a 50
r esi stor and ap p y the si g nal d ectl y to IN P
W20
VOSADJ
Analog Voltage Input to Adjust the Converter Offset. This input accepts an input-voltage range of
0 to 2.5V allowing the offset to be adjusted at roughly ±10 LSB.
M4
DORP
True/Positive LVDS Data-Overrange Output Bit. This output flags over- and under-range
conditions of the data converter.
M3
DORN
Complementary/Negative LVDS Data-Overrange Output Bit. This output flags over- and under-
range conditions on the data converter.
M2
DCOP
True/Positive LVDS Data Clock Output. Synchronize user-supplied data-capture board or data-
acquisition system to this clock.
M1
DCON
Complementary/Negative LVDS Data Clock Output. Synchronize user-supplied data-capture
board or data-acquisition system to this clock.
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