參數(shù)資料
型號(hào)： MAX1088EKA-T
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi)： ADC
英文描述： 150ksps, 10-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs in SOT23
中文描述： 2-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
封裝： SOT-23, 8 PIN
文件頁(yè)數(shù)： 12/15頁(yè)
文件大?。?/td> 334K
代理商： MAX1088EKA-T
M
the first eight data bits starting with the MSB. The sec-
ond 8-bit data stream contains the remaining bits, D1
through D0, and the two sub-bits S1 and S0.
Layout, Grounding, and Bypassing
For best performance, use printed circuit (PC) boards.
Wire-wrap configurations are not recommended since
the layout should ensure proper separation of analog
and digital traces. Do not run analog and digital lines
parallel to each other, and do not lay out digital signal
paths underneath the ADC package. Use separate
analog and digital PC board ground sections with only
one starpoint (Figure 11), connecting the two ground
systems (analog and digital). For lowest-noise opera-
tion, ensure the ground return to the star ground
’
s
power supply is low impedance and as short as possi-
ble. Route digital signals far away from sensitive analog
and reference inputs.
High-frequency noise in the power supply (V
DD
) may
degrade the performance of the ADC
’
s fast comparator.
Bypass V
DD
to the star ground with a 0.1μF capacitor,
located as close as possible to the MAX1086
–
MAX1089s
power supply pin. Minimize capacitor lead length for best
supply-noise rejection. Add an attenuation resistor (5
) if
the power supply is extremely noisy.
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23
12
______________________________________________________________________________________
CNVST
SCLK
DOUT
CS
SCK
MISO
V
DD
SS
QSPI
MAX1086
–
MAX1089
Figure 9a. QSPI Connections
Table 2. Detailed SSPSTAT Register Content
X = Don
’
t care
D/A
P
S
R/W
UA
BF
CONTROL BIT
MAX1086
–
MAX1089
SETTINGS
SYNCHRONOUS SERIAL STATUS REGISTER (SSPSTAT)
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
Data Address Bit
Stop Bit
Start Bit
Read/Write Bit Information
SMP
Bit 7
0
SPI Data Input Sample Phase. Input data is sampled at the middle of the data output
time.
CKE
Bit 6
1
SPI Clock Edge Select Bit. Data will be transmitted on the rising edge of the serial clock.
Buffer Full Status Bit
Update Address
Figure 8c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0)
CNVST
1ST BYTE READ
SCLK
DOUT
2ND BYTE READ
SAMPLING INSTANT
4
1
8
12
B9
MSB
B8
B7
B6
B5
B4
B3
B2
B1
B0
LSB
S1
S0
HIGH-Z
16
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