參數(shù)資料
型號(hào): MAX107ECS+T
廠(chǎng)商: Maxim Integrated Products
文件頁(yè)數(shù): 6/21頁(yè)
文件大?。?/td> 0K
描述: IC ADC 6BIT 400MSPS DL 80-TQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1,000
位數(shù): 6
采樣率(每秒): 400M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 2.6W
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 80-TQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 80-TQFP-EP(12x12)
包裝: 帶卷 (TR)
輸入數(shù)目和類(lèi)型: 4 個(gè)單端,雙極;2 個(gè)差分,雙極
MAX107
designed for single-ended, low-phase noise sine-wave
clock signals with as little as 500mVp-p amplitude
(-2dBm).
Single-Ended Clock (Sine-Wave Drive)
Excellent performance is obtained by AC- or DC-cou-
pling a low-phase noise sine-wave source into a single
clock input (Figure 4). Essentially, the dynamic perfor-
mance of the converter is unaffected by clock-drive
power levels from -2dBm (500mVp-p clock signal
amplitude) to +10dBm (2Vp-p clock signal amplitude).
The MAX107 dynamic performance specifications are
determined by a single-ended clock drive of -2dBm
(500mVp-p clock signal amplitude). To avoid saturation
of the input amplifier stage, limit the clock power level
to a maximum of +10dBm.
Differential Clock (Sine-Wave Drive)
The advantages of differential clock drive (Figure 5)
can be obtained by using an appropriate balun or
transformer to convert single-ended sine-wave sources
into differential drives. Refer to Single-Ended Clock
Inputs (Sine-Wave Drive) for proper input amplitude
requirements.
LVDS, ECL and PECL Clock
The innovative input architecture of the MAX107 clock
also allows these inputs to be driven by LVDS-, ECL- or
PECL-compatible input levels, ranging from 500mVp-p
to 2Vp-p (Figure 6).
Timing Requirements
The MAX107 features a 6:12 demultiplexer, which
reduces the output data rate (including DREADY and
DOR signals) to one-half of the sample clock rate. The
demultiplexed outputs are presented in dual 6-bit two’s
complement format with two consecutive samples in
the primary and auxiliary output ports on the rising
Dual, 6-Bit, 400Msps ADC with On-Chip,
Wideband Input Amplifier
14
______________________________________________________________________________________
AGND
B
0
°
0
°
0
°
180
°
D
C
A
SIGNAL SOURCE
50
*TERMINATION OF THE UNUSED INPUT/OUTPUT (WITH 50
TO AGND) ON A
BALUN IS RECOMMENDED IN ORDER TO AVOID UNWANTED REFLECTIONS.
CLK+,
INI+,
INQ+
CLK-,
INI-,
INQ-
100pF
50
50
AGND
50
*
Figure 3. Single-Ended to Differential Conversion Using a Balun
AGND
FROM SIGNAL SOURCE
CLK+,
INI+,
INQ+
CLK-,
INI-,
INQ-
100pF
50
Figure 4. Single-Ended Clock Input With AC-Coupled Input
Drive (CLK, INI, INQ)
Figure 5. Differential, AC-Coupled Input Drive (CLK, INI, INQ)
AGND
50
TRANSMISSION LINES
TO 50
-TERMINATED
SIGNAL SOURCE
OR BALUN
CLK+,
INI+,
INQ+
CLK-,
INI-,
INQ-
100pF
50
50
50
TRANSMISSION LINES
LVDS LINE DRIVER
SIGNAL
SOURCE
INPUT
CLK+,
INI+,
INQ+
CLK-,
INI-,
INQ-
100pF
100
Figure 6. LVDS Input Drive (CLK, INI, INQ)
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MAX1080 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit ADCs with Internal Reference
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