clock design limits aperture jitter to typically 1.5psRMS. Figu" />
參數(shù)資料
型號: MAX107ECS+T
廠商: Maxim Integrated Products
文件頁數(shù): 11/21頁
文件大?。?/td> 0K
描述: IC ADC 6BIT 400MSPS DL 80-TQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1,000
位數(shù): 6
采樣率(每秒): 400M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 2.6W
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 80-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 80-TQFP-EP(12x12)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 4 個單端,雙極;2 個差分,雙極
clock design limits aperture jitter to typically 1.5psRMS.
Figure 11 depicts the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.
Aperture delay (tAD) is the time defined between the
rising edge of the sampling clock and the instant when
an actual sample is taken (Figure 11).
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza-
tion error only and results directly from the ADC’s reso-
lution (N-Bits):
SNRMAX[dB] = 6.02dB x N + 1.76dB
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter
(see Aperture Uncertainties). SNR is computed by tak-
ing the ratio of the RMS signal to the RMS noise, which
includes all spectral components minus the fundamen-
tal, the first four harmonics, and the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS sig-
nal to all spectral components minus the fundamental
and the DC offset.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at
a specific input frequency, amplitude, and sampling
rate relative to an ideal ADC’s quantization noise. For a
full-scale input ENOB is computed from:
ENOB = (SINAD - 1.76dB) / 6.02dB
Total Harmonic Distortion (THD)
THD is typically the ratio of the RMS sum of the first four
harmonics of the input signal to the fundamental itself.
This is expressed as:
where V1 is the fundamental amplitude, and V2 through
V
5 are the amplitudes of the 2nd- through 5th-order har-
monics.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental to the RMS value of the
next largest spurious component, excluding DC offset.
Two-Tone Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst 3rd-order (or higher) inter-
modulation products. The individual input tone levels
are at -7dB full-scale and their envelope peaks at -1dB
full-scale.
Chip Information
TRANSISTOR COUNT: 12,286
THD
x
V
=+
+
20
2
3
2
4
2
5
2
1
2
log (
) /
)
MAX107
Dual, 6-Bit, 400Msps ADC with On-Chip,
Wideband Input Amplifier
______________________________________________________________________________________
19
CLK+
ANALOG
INPUT
SAMPLING
INSTANT
tAW
tAD
tAJ
CLK-
tAW: APERTURE WIDTH
tAJ: APERTURE JITTER
tAD: APERTURE DELAY
Figure 11. Aperture Timing
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