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參數(shù)資料
| 型號： | MAX107 |
| 廠商： | Maxim Integrated Products, Inc. |
| 元件分類： | ADC |
| 英文描述： | Dual, 6-Bit, 400Msps ADC with On-Chip, Wideband Input Amplifier |
| 中文描述： | 雙路、6位、400Msps ADC，帶有片上寬帶輸入放大器 |
| 文件頁數(shù)： | 5/21頁 |
| 文件大?。?/td> | 1423K |
| 代理商： | MAX107 |
M
Dual, 6-Bit, 400Msps ADC with On-Chip,
Wideband Input Amplifier
_______________________________________________________________________________________
5
Note 1:
Note 2:
Note 3:
INL and DNL is measured using a sine-histogram method.
Input offset is the voltage required to cause a transition between codes 0 and -1.
Numbers provided are for DC-coupled case. The user has the choice of AC-coupling, in which case, the DC input voltage
level does not matter.
The peak-to-peak input voltage required, causing a full-scale digitized output when using a trigonometric curve-fitting algo
rithm (e.g. FFT).
Guaranteed by design and characterization.
Common-mode rejection ratio is defined as the ratio of the change in the offset voltage to the change in the common-mode
voltage expressed in dB.
Measured with analog power supplies tied to the same potential.
Effective number of bits (ENOB) is computed from a curve-fit referenced to the theoretical full-scale range.
The clock and input frequencies are chosen so that there are 2041 cycles in an 8,192-long record.
Note 10:
Signal-to-noise-ratio (SNR) is measured both with the other channel idling and converting an out-of-phase signal.
The worst case number is presented. Harmonic distortion components two through five are excluded from the noise.
Note 11:
Harmonic distortion components two through five are included in the total harmonic distortion specification.
Note 12:
Both I and Q inputs are effectively tied together (e.g. driven by power splitter). Signal amplitude is -0.5dB FS at an input
frequency of f
IN
= 124.999 MHz.
Note 13:
Measured with a differential probe, 1pF capacitance.
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
ELECTRICAL CHARACTERISTICS (continued)
(AV
CC
= AV
CC
I = AV
CC
Q = AV
CC
R = +5V, OV
CC
I = OV
CC
Q = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ
= 0, f
CLK
= 401.408MHz, C
L
= 1μF to AGND at REF, R
L
= 100
±1% applied to digital LVDS outputs, T
A
= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at T
A
= +25
°
C)
PARAMETER
SYMBOL
CONDITIONS
MIN
47
200
200
TYP
MAX
53
500
500
UNITS
%
ps
ps
DREADY Duty Cycle
LVDS Output Rise-Time
LVDS Output Fall-Time
(Notes 5, 13)
20% to 80% (Notes 5, 13)
20% to 80% (Notes 5, 13)
Any differential pair
Any tw o LV D S outp ut si g nal s excep D RE AD Y
20% to 80% (Notes 5, 13)
20% to 80% (Notes 5, 13)
t
RDATA
t
FDATA
<65
<100
LVDS Differential Skew
t
SKEW1
ps
DREADY Rise-Time
DREADY Fall-Time
t
RDREADY
t
FDREADY
200
200
500
500
ps
ps
Primary Port Pipeline Delay
t
PDP
5
Clock
Cycles
Auxiliary Port Pipeline Delay
t
PDA
6
Clock
Cycles
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