參數(shù)資料
型號(hào)： MAX1067CEEE
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： ADC
英文描述： Multichannel, 14-Bit, 200ksps Analog-to-Digital Converters
中文描述： 4-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16
封裝： 0.150 INCH, 0.250 INCH PITCH, MO-137AB, QSOP-16
文件頁(yè)數(shù)： 18/30頁(yè)
文件大?。?/td> 447K
代理商： MAX1067CEEE
M
prior to the rising edge of
CS
, cause zeros to be
clocked out of DOUT. The MAX1068 external clock 16-
bit-wide data-transfer mode requires 32 SCLK cycles for
completion (Figure 11).
Force
CS
high after the conversion result is read. For
maximum throughput, force
CS
low again to initiate the
next conversion immediately after the specified mini-
mum time (t
CSW
). Forcing
CS
high in the middle of a
conversion immediately aborts the conversion and
places the MAX1068 in shutdown.
Internal Clock 8-Bit-Wide Data-Transfer and
Scan Mode (MAX1067 and MAX1068)
Force DSPR high and DSEL low (MAX1068) for the SPI/
QSPI/MICROWIRE-interface mode. The falling edge of
CS
wakes the analog circuitry and allows SCLK to
clock in data (Figure 12). DOUT changes from high-Z
to logic low after
CS
is brought low. Input data latches
on the rising edge of SCLK. The command/configura-
tion/control register begins reading DIN on the first
SCLK rising edge and ends on the rising edge of the
8th SCLK cycle. The MAX1067/MAX1068 select the
proper channel for conversion on the rising edge of the
3rd SCLK cycle. The internal oscillator activates 125ns
after the rising edge of the 8th SCLK cycle. Turn off the
external clock while the internal clock is on. Turning off
SCLK ensures the lowest noise performance during
acquisition. Acquisition begins on the 2nd rising edge
of the internal clock and ends on the falling edge of the
6th internal clock cycle. Each bit of the conversion
result shifts into memory as it becomes available. The
conversion result is available (MSB first) at DOUT on
the falling edge of
EOC
. The internal oscillator and ana-
log circuitry are shut down on the high-to-low
EOC
tran-
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
18
______________________________________________________________________________________
DOUT
CS
SCLK
DIN
DSPR
DSEL
0
MSB
LSB
MSB
LSB
S1
S0
ADC
STATE
16
24
32
1
8
X
X
X
X
X
X
X
X
X = DON,T CARE
t
ACQ
IDLE
t
CONV
Figure 11. SPI External Clock Mode, 16-Bit Data-Transfer Mode, Conversion Timing (MAX1068 Only)
DOUT
CS
SCLK
DIN
EOC
1
MSB
LSB
LSB
S1
S0
X
t
ACQ
IDLE
t
CONV
POWER-DOWN
ADC
STATE
X = DON,T CARE
DSPR = DV
DD
, DSEL = GND (MAX1068 ONLY)
INTERNAL
CLK
1
8
2
6
25
16
9
24
MSB
Figure 12. SPI Internal Clock Mode, 8-Bit Data-Transfer Mode, Conversion Timing
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MAX1067CEEE-T 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX1068 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:MAX1168 Evaluation Kit/Evaluation System
MAX1068ACEG 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX1068ACEG+ 功能描述:模數(shù)轉(zhuǎn)換器 - ADC MultiCh 14-Bit 200ksps RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX1068ACEG+T 功能描述:模數(shù)轉(zhuǎn)換器 - ADC MultiCh 14-Bit 200ksps RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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