參數(shù)資料
型號(hào)： MAX105
廠商： Maxim Integrated Products, Inc.
英文描述： Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier
中文描述： 雙路、6位、800Msps ADC，帶有片上寬帶輸入放大器
文件頁(yè)數(shù)： 4/21頁(yè)
文件大?。?/td> 669K
代理商： MAX105
M
Dual, 6-Bit, 800Msps ADC with On-Chip,
Wideband Input Amplifier
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AV
CC
= AV
CC
I = AV
CC
Q = AV
CC
R = +5V, OV
CC
I = OV
CC
Q = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ
= 0, f
CLK
= 802.816MHz, C
L
= 1μF to AGND at REF, R
L
= 100
±1% applied to digital LVDS outputs, T
A
= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at T
A
= +25
°
C)
PARAMETER
SYMBOL
CONDITIONS
MIN
34
TYP
36.4
36.1
MAX
UNITS
Differential
Single-ended
f
IN
= 200.018MHz at
-0.5dB FS (Note 9)
Signal-to-Noise Plus Distortion
Ratio
SINAD
f
IN
= 400.134MHz at
-0.5dB FS
Differential
35.2
dB
Two-Tone Intermodulation
TTIMD
f
IN1
= 124.1660MHz, f
IN2
= 126.1260MHz
at -7dBFS
-52
dBc
Crosstalk Between ADCs
XTLK
f
INI
= 200.0180MHz, f
INQ
= 210.0140MHz
at -0.5dB FS
-70
dB
Gain Match Between ADCs
Phase Match Between ADCs
GM
PM
(Note 12)
(Note 12)
-0.3
-2
±
0.04
±
0.2
+0.3
+2
dB
deg
Metastable Error Rate
Less than 1 in 10
16
Clock
Cycles
POWER REQUIREMENTS
Analog Supply Voltage
Digital Supply Voltage
Analog Supply Current
Output Supply Current
Analog Power Dissipation
C om m on- M od e Rej ecti on Rati o
AV
CC_
OV
CC_
I
CC
OI
CC
P
DISS
CMRR
AV
CC
= AV
CC
I = AV
CC
Q = AV
CC
R
OV
CC
I = OV
CC
Q
I
CC
= AI
CC
R + AI
CC
I + AI
CC
Q + AI
CC
OI
CC
= OI
CC
I + OI
CC
Q
5
±
5%
3.3
±
10%
250
400
2.6
60
V
V
320
510
mA
mA
W
dB
V
IN_+
= V
IN_-
=
±
0.1V (Note 6)
AV
CC
= AV
CC
I = AV
CC
Q = AV
CC
R =
+4.75V to +5.25V (Note 7)
40
Power-Supply Rejection Ratio
PSRR
40
57
dB
TIMING CHARACTERISTICS
Maximum Sample Rate
Clock Pulse Width Low
Clock Pulse Width High
Aperture Delay
Aperture Jitter
f
MAX
t
PWL
t
PWH
t
AD
t
AJ
800
0.56
0.56
Msps
ns
ns
ps
ps
RMS
100
1.5
CLK-to-DREADY Propagation
Delay
t
PD1
(Note 13)
1.5
ns
DREADY-to-DATA
Propagation Delay
t
PD2
(Notes 5, 13)
0
120
300
ps
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