參數(shù)資料
型號(hào): MAX1021BETX+
廠商: Maxim Integrated Products
文件頁數(shù): 7/40頁
文件大?。?/td> 0K
描述: IC ADC/DAC 10BIT W/FIFO 36-TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 50
類型: ADC,DAC
分辨率(位): 10 b
采樣率(每秒): 300k
數(shù)據(jù)接口: 串行
電壓電源: 模擬和數(shù)字
電源電壓: 2.7V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 36-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 36-TQFN 裸露焊盤(6x6)
包裝: 管件
MAX1021/MAX1043
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
______________________________________________________________________________________
15
Pin Description
PIN
MAX1021
MAX1043
NAME
FUNCTION
1, 2
GPIOA0, GPIOA1 General-Purpose I/O A0, A1. GPIOA0, GPIOA1 can sink and source 15mA.
33
EOC
Active-Low, End-of-Conversion Output. Data is valid after the falling edge of
EOC.
44DVDD
Digital Positive-Power Input. Bypass DVDD to DGND with a 0.1F capacitor.
5
DGND
Digital Ground. Connect DGND to AGND.
6
DOUT
Serial-Data Output. Data is clocked out on the falling edge of the SCLK clock in
modes 00, 01, and 10. Data is clocked out on the rising edge of the SCLK clock
in mode 11. It is high impedance when
CS is high.
77SCLK
Serial-Clock Input. Clocks data in and out of the serial interface. (Duty cycle must be
40% to 60%). See Table 5 for details on programming the clock mode.
88
DIN
Serial-Data Input. DIN data is latched into the serial interface on the falling edge
of SCLK.
9–12
OUT0–OUT3
DAC Outputs
9–12, 16–19
OUT0–OUT7
DAC Outputs
13
AVDD
Positive Analog Power Input. Bypass AVDD to AGND with a 0.1F capacitor.
14
AGND
Analog Ground
15, 23, 32, 33
N.C.
No Connection. Not internally connected.
20
LDAC
Active-Low, Load DAC.
LDAC is an asynchronous active-low input that updates
the DAC outputs. Drive
LDAC low to make the DAC registers transparent.
21
CS
Active-Low, Chip-Select Input. When
CS is low, the serial interface is enabled.
When
CS is high, DOUT is high impedance.
22
RES_SEL
Reset Select. Select DAC wake-up mode. Set RES_SEL low to wake up the DAC
outputs with a 100k
Ω resistor to GND or set RES_SEL high to wake up the DAC outputs
with a 100k
Ω resistor to VREF. The default is the external VREF.
24, 25
GPIOC0, GPIOC1 General-Purpose I/O C0, C1. GPIOC0, GPIOC1 can sink 4mA and source 2mA.
26
REF1
Reference 1 Input. Reference voltage; leave unconnected to use the internal
reference (2.5V). REF1 is the positive reference in ADC differential mode. Bypass
REF1 to AGND with a 0.1F capacitor in external reference mode only. See the
ADC/DAC References section.
27–31, 34
AIN0–AIN5
Analog Inputs
35
REF2/AIN6
Reference 2 Input/Analog Input Channel 6. See Table 5 for details on
programming the setup register.
36
CNVST/AIN7
Active-Low, Conversion-Start Input/Analog Input 7. See Table 5 for details on
programming the setup register.
16-19
D.C.
Do Not Connect. Do not connect to this pin.
——
EP
Exposed Pad. Must be externally connected to AGND. Do not use as a ground
connect.
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