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參數(shù)資料
| 型號(hào)： | MAX100 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 250Msps, 8-Bit ADC with Track/Hold(250Msps,單通道，并行,8位模數(shù)轉(zhuǎn)換器) |
| 中文描述： | 250Msps、8位ADC，帶有采樣/保持 |
| 文件頁(yè)數(shù)： | 11/16頁(yè) |
| 文件大?。?/td> | 159K |
| 代理商： | MAX100 |
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M
250Msps, 8-Bit ADC with Trac k/Hold
______________________________________________________________________________________
11
_______________Detailed Desc ription
Converter Operation
The parallel or “flash” architecture used by the MAX100
provides the fastest multibit conversion of all common
integrated ADC designs. The basic element of a flash
(as with all other ADC architectures) is the comparator,
which has a positive input, a negative input, and an
output. If the voltage at the positive input is higher than
the negative input (connected to a reference), the out-
put will be high. If the positive input voltage is lower
than the reference, the output will be low. A typical n-
bit flash consists of 2
n
-1 comparators with negative
inputs evenly spaced at 1LSB increments from the bot-
tom to the top of the reference ladder. For n = 8, there
will be 255 comparators.
For any input voltage, all the comparators with negative
inputs connected to the reference ladder below the
input voltage will have outputs of 1, and all compara-
tors with negative inputs above the input voltage will
have outputs of 0. Decode logic is provided to convert
this information into a parallel n-bit digital word (the out-
put) corresponding to the number of LSBs (minus 1)
that the input voltage is above the level set at the bot-
tom of the ladder.
Finally, the comparators contain latch circuitry and are
clocked. This allows the comparators to function as
described above when, for example, clock is low.
When clock goes high (samples) the comparator will
latch and hold its state until the clock goes low again.
T rac k/Hold
As with all ADCs, if the input waveform is changing
rapidly during the conversion the effective bits and
SNR will decrease. The MAX100 has an internal
track/hold (T/H) that increases attainable effective-bits
performance and allows more accurate capture of ana-
log data at high conversion rates.
The internal T/H circuit provides two important circuit
functions for the MAX100:
1) Its nominal voltage gain of 4 reduces the input dri-
ving signal to ±270mV differential (assuming a
±1.02V reference).
2) It provides a differential 50
input that allows easy
interface to the MAX100.
Data Flow
The MAX100 contains an internal T/H amplifier that
stores the analog input voltage for the ADC to convert.
The differential inputs AIN+ and AIN- are tracked con-
tinuously between data samples. When a negative CLK
edge is applied, the T/H enters hold mode (Figure 5).
When CLK goes low, the most recent sample is pre-
sented to the ADC’s input comparators. Internal pro-
cessing of the sampled data is delayed for several
clock cycles before it is available at outputs AData or
BData. All output data is timed with respect to DCLK
and DCLK (Figures 1–4).
__________Applic ations Information
Analog Input Ranges
Although the normal operating range is ±270mV, the
MAX100 can be operated with up to ±500mV on each
input with respect to ground. This extended input level
includes the analog signal and any DC common-mode
voltage.
To obtain a full-scale digital output with differential input
drive, a nominal +270mV must be applied between
AIN+ and AIN-. That is, AIN+ = +135mV and AIN- =
-135mV (with no DC offset). Mid-scale digital output
code occurs when there is no voltage difference across
the analog inputs. Zero-scale digital output code, with
differential -270mV drive, occurs when AIN+ = -135mV
and AIN- = +135mV. Table 2 shows how the output of
the converter stays at all ones (full scale) when over
ranged or all zeros (zero scale) when under ranged.
For single-ended operation:
1) Apply a DC offset to one of the analog inputs, or
leave one input open. (Both AIN+ and AIN- are ter-
minated internally with 50
to analog ground.)
2) Drive the other input with a ±270mV + offset to
obtain either full- or zero-scale digital output. If a DC
common-mode offset is used, the total voltage swing
allowed is ±500mV (analog signal plus offset with
respect to ground).
Table 1. Input Voltage Range
**An offset V
IO
, as specified in the DC electrical parameters, may
be present at the input. Compensate for this offset by either
adjusting the reference voltage (VA
RT
or VA
RB
), or introducing an
offset voltage in one of the input terminals AIN + or AIN-.
+135
0
-135
+270
0
-270
-135
0
+135
0
0
0
AIN+**
(mV)
AIN-**
(mV)
INPUT
11111111
10000000
00000000
11111111
10000000
00000000
OUTPUT
CODE
full scale
mid scale
zero scale
full scale
mid scale
zero scale
MSB to LSB
Single
Ended
Differential
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX-100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:HIGH CURRENT TRANSIENT VOLTAGE SUPPRESSOR |
| MAX1002 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Low-Power, 60Msps, Dual, 6-Bit ADC |
| MAX1002CAX | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1002CAX+ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Low-Power 60Msps Dual 6-Bit RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1002CAX+T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Low-Power 60Msps Dual 6-Bit RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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