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參數(shù)資料
| 型號： | MAX1007 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Mobile-Radio Analog Controller |
| 中文描述： | 移動無線模擬控制器 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 110K |
| 代理商： | MAX1007 |
M
by the counter. Data is clocked into DIN or the falling
edge of SCLK, and is clocked out of DOUT on SCLK’s
rising edge. The serial interface is always active.
The SCLK and DIN idle state is low (Figure 4). The first
“1” clocked in after
CS
goes low is the start bit, signify-
ing the beginning of a 16-bit data word. The command
and data input registers are cleared and the counter is
started. The next 7 bits are latched in the command
register.
Command Byte
The command byte (Figure 4d) consists of three
address bits (A2, A1, A0), two power-mode bits (RxEN,
TxEN), a shutdown control bit (SD), and a load data bit
(LD). Table 1 lists the address and data-byte defini-
tions.
SD is the software control for the GaAs FET bias gener-
ator shutdown pin and GDAC. Resetting SD to “0”
causes
SDG
to go low and disables GDAC. The
SDG
output is updated if LD is set high.
LD is the software control to update the output regis-
ters. During a write operation, the addressed DAC’s
input buffer is updated. With LD reset to “0,” the DAC
register and DAC output remain unchanged. With LD
set to “1,” all DACs and power-class registers are
simultaneously updated to the values in their input reg-
isters immediately after the last data bit (including DAC
values, power-class bits, F/R bit, RSSI and ADC input
selections,
SDG
, and power-down bits).
After a 16-bit read cycle, pull
CS
high. The interface is
now ready for a new command sequence. During a
read operation, the ADC conversion result is output to
DOUT. With LD set to “1,” all other outputs and power-
class registers are also updated.
Write Command
The 8 data bits are latched in the data input register.
The command byte is decoded, and the data bits are
transferred to the appropriate registers.
Read Command
After the command byte is decoded, the last 8 clocks
output data, MSB first, from the ADC output register to
DOUT (Figure 4b). After a 16-bit read cycle, pull
CS
high. The interface is now ready for a new command
sequence.
To minimize the delay between the power-sense measure-
ment and the ADC output, program a ‘READ ADC’ com-
mand prior to making the power-sense measurement and
clock out the data as soon as the conversion is complete
(Figure 4b). This reduces the delay by 8 clock cycles.
To minimize the delay between the power-sense measure-
ment and the ADC output, program a “READ ADC” com-
mand prior to making the power-sense measurement and
clock out the data as soon as the conversion is complete
(Figure 4b). This reduces the delay by F clock cycles.
Mobile-Radio Analog Controller
10
______________________________________________________________________________________
CS
SCLK
ACTIVE ADC
DOUT
CLOCK COMMAND
BYTE INTODIN
WRITE A
“READ ADC”
COMMAND
CLOCK CONVERSION
DATA ONTODOUT
ADC CONVERSION DATA
t
9
POWER-SENSE
MEASUREMENTS
CLOCK OUT
CONVERSION
RESULT
Figure 4b. Clock Command Conversion
READ
CS
SCLK
DOUT
t
3
t
4
t
5
t
8
t
6
t
7
WRITE
SCLK
DIN
t
1
t
2
Figure 4a. Read/Write Detailed Interface Timing
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