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參數(shù)資料
| 型號： | MACH220-20 |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PLD |
| 英文描述： | High-Density EE CMOS Programmable Logic |
| 中文描述： | EE PLD, PQCC68 |
| 文件頁數(shù)： | 1/33頁 |
| 文件大?。?/td> | 230K |
| 代理商： | MACH220-20 |
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Publication#
14130
Issue Date:
May 1995
Rev.
I
Amendment
/0
Advanced
Micro
Devices
MACH220-10/12/15/20
High-Density EE CMOS Programmable Logic
FINAL
COM’L: -10/12/15/20
IND: -14/18/24
DISTINCTIVE CHARACTERISTICS
68 Pins
96 Macrocells
10 ns t
PD
100 MHz f
CNT
56 Inputs with pull-up resistors
48 Outputs
96 Flip-flops; 4 clock choices
8 “PAL26V12” blocks with buried macrocells
Pin-compatible with MACH120 and MACH221
GENERAL DESCRIPTION
The MACH220 is a member of AMD’s high-performance
EE CMOS MACH 2 device family. This device has
approximately nine times the logic macrocell capability
of the popular PAL22V10 without loss of speed.
The MACH220 consists of eight PAL blocks intercon-
nected by a programmable switch matrix. The eight PAL
blocks are essentially “PAL26V12” structures complete
with product-term arrays, and programmable macro-
cells, including buried macrocells. The switch matrix
connects the PAL blocks to each other and to all input
pins, providing a high degree of connectivity between
the fully-connected PAL blocks. This allows designs to
be placed and routed efficiently.
The MACH220 has two kinds of macrocell: output and
buried. The output macrocell provides registered,
latched, or combinatorial outputs with programmable
polarity. If a registered configuration is chosen, the
register can be configured as D-type or T-type to help
reduce the number of product terms. The register type
decision can be made by the designer or by the
software. All output macrocells can be connected to an
I/O cell. If a buried macrocell is desired, the internal
feedback path from the macrocell can be used, which
frees up the I/O pin for use as an input.
The MACH220 has dedicated buried macrocells which,
in addition to the capabilities of the output macrocell,
also provide input registers for use in synchronizing
signals and reducing setup time requirements.
BLOCK DIAGRAM
If you would like to view
Block Diagram in full size,
please click on the box.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MACH220-20JI | High-Density EE CMOS Programmable Logic |
| MAX542 | Quadruple Bus Buffer Gate With 3-State Outputs 14-PDIP -40 to 85 |
| MAX542ACPD | +5V, Serial-Input, Voltage-Output, 16-Bit DACs |
| MAX542ACSD | +5V, Serial-Input, Voltage-Output, 16-Bit DACs |
| MAX542AEPD | +5V, Serial-Input, Voltage-Output, 16-Bit DACs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MACH220-20JC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MACH220-20JI | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:High-Density EE CMOS Programmable Logic |
| MACH221-10JC | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Performance EE CMOS Programmable Logic |
| MACH221-10JI | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Performance EE CMOS Programmable Logic |
| MACH221-12JC | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Performance EE CMOS Programmable Logic |
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