參數(shù)資料
型號(hào)： MAX542
廠商： Advanced Micro Devices, Inc.
英文描述： Quadruple Bus Buffer Gate With 3-State Outputs 14-PDIP -40 to 85
中文描述： +5V、串行輸入、電壓輸出16位DAC
文件頁(yè)數(shù)： 1/35頁(yè)
文件大?。?/td> 493K
代理商： MAX542
FINAL
Publication#
11560
Issue Date:
January 1998
Rev:
G
Amendment/
+2
Am28F256
256 Kilobit (32 K x 8-Bit)
CMOS 12.0 Volt, Bulk Erase Flash Memory
DISTINCTIVE CHARACTERISTICS
I
High performance
— 70 ns maximum access time
I
CMOS Low power consumption
— 30 mA maximum active current
— 100 μA maximum standby current
— No data retention power consumption
I
Compatible with JEDEC-standard byte-wide
32-Pin EPROM pinouts
— 32-pin PDIP
— 32-pin PLCC
— 32-pin TSOP
I
10,000 write/erase cycles minimum
I
Write and erase voltage 12.0 V
±
5%
I
Latch-up protected to 100 mA
from –1 V to V
CC
+1 V
I
Flasherase
Electrical Bulk Chip-Erase
— One second typical chip-erase
I
Flashrite Programming
— 10 μs typical byte-program
— 0.5 second typical chip program
I
Command register architecture for
microprocessor/microcontroller compatible
write interface
I
On-chip address and data latches
I
Advanced CMOS flash memory technology
— Low cost single transistor memory cell
I
Automatic write/erase pulse stop timer
GENERAL DESCRIPTION
The Am28F256 is a 256 K Flash memory organized as
32 Kbytes of 8 bits each. AMD’s Flash memories offer
the most cost-effective and reliable read/write non-
volatile random access memory. The Am28F256 is
packaged in 32-pin PDIP PLCC, and TSOP versions. It
is designed to be reprogrammed and erased in-system
or in standard EPROM programmers. The Am28F256
is erased when shipped from the factory.
The standard Am28F256 offers access times as fast as
70 ns, allowing operation of high-speed microproces-
sors without wait states. To eliminate bus contention,
the Am28F256 has separate chip enable (CE
#
) and
output enable (OE
#
) controls.
AMD’s Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
Am28F256 uses a command register to manage this
functionality, while maintaining a standard JEDEC
Flash Standard 32-pin pinout. The command register
allows for 100% TTL level control inputs and fixed
power supply levels during erase and programming.
AMD’s Flash technology reliably stores memory
contents even after 10,000 erase and program cycles.
The AMD cell is designed to optimize the erase and
programming mechanisms. In addition, the combina-
tion of advanced tunnel oxide processing and low
internal electric fields for erase and programming
operations produces reliable cycling. The Am28F256
uses a 12.0V
±
5% V
PP
high voltage input to perform
the Flasherase
and Flashrite
algorithms.
The highest degree of latch-up protection is achieved
with AMD’s proprietary non-epi process. Latch-up
protection is provided for stresses up to 100 milliamps
on address and data pins from –1 V to V
CC
+1 V.
The Am28F256 is byte programmable using 10 μs
programming pulses in accordance with AMD’s
Flashrite programming algorithm. The typical room
temperature programming time of the Am28F256 is a
half a second. The entire chip is bulk erased using
10 ms erase pulses according to AMD’s Flasherase
alrogithm. Typical erasure at room temperature is
accomplished in less than one second. The windowed
package and the 15-20 minutes required for EPROM
erasure using ultra-violet light are eliminated.
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