參數(shù)資料
型號(hào)： MAC7136VVM50
廠商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 50 MHz, RISC MICROCONTROLLER, PBGA208
封裝： 17 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, MAPBGA-208
文件頁(yè)數(shù)： 22/56頁(yè)
文件大?。?/td> 1216K
代理商： MAC7136VVM50
ElectricalCharacteristics
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
Freescale Semiconductor
29
3.11 Serial Peripheral Interface
3.11.1 Master Mode
Master mode timing values are shown in Table 32 and illustrated in Figure 11 and Figure 12.
3.11.2 Slave Mode
Slave mode timing values are shown in Table 33 and illustrated in Figure 13 and Figure 14.
Table 32. SPI Master Mode Timing Characteristics
Conditions are shown in Table 7 unless otherwise noted, CLOAD = 200 pF on all outputs
Num C
Rating
Symbol
Min
Typ
Max
Unit
U1a
P Operating Frequency (baud rate)
fOP
1
NOTES:
1. Refer to MAC7100 Microcontroller Family Reference Manual (MAC7100RM) Chapter 22 for all available baud rates.
— 2
2. On mask set L49P and L47W devices, U1a maximum = and U1b minimum = 4.
fIPS
U1b
P SCK Period (tSCK = 1 ÷ fOP, tIPS = 1 ÷ fIPS)tSCK
2 2
—7
× 32,768
tIPS
U2
D Enable Lead Time
tlead
—
tSCK
U3
D Enable Lag Time
tlag
—
tSCK
U4
D Clock (SCK) High or Low Time
twsck
tIPS 30
—
1024 tIPS
ns
U5
D Data Setup Time (Inputs)
tsu
25
—
ns
U6
D Data Hold Time (Inputs)
thi
0—
—
ns
U9
D Data Valid (after Enable Edge)
tv
——
25
ns
U10
D Data Hold Time (Outputs)
tho
0—
—
ns
U11
D Rise Time Inputs and Outputs
tr
——
25
ns
U12
D Fall Time Inputs and Outputs
tf
——
25
ns
Table 33. SPI Slave Mode Timing Characteristics
Conditions are shown in Table 7 unless otherwise noted, CLOAD = 200 pF on all outputs
Num C
Rating
Symbol
Min
Typ
Max
Unit
V1a
P Operating Frequency
fOP
— 1
NOTES:
1. On mask set L49P and L47W devices, V1a maximum = and V1b minimum = 4.
fIPS
V1b
P SCK Period (tSCK = 1 ÷ fOP, tIPS = 1 ÷ fIPS)tSCK
2 1
—7
× 32,768
tIPS
V2
D Enable Lead Time
tlead
1—
—
tIPS
V3
D Enable Lag Time
tlag
1—
—
tIPS
V4
D Clock (SCK) High or Low Time
twsck
tIPS 30
—
ns
V5
D Data Setup Time (Inputs)
tsu
25
—
ns
V6
D Data Hold Time (Inputs)
thi
25
—
ns
V7
D Slave Access Time
ta
——
1
tIPS
V8
D Slave SIN Disable Time
tdis
——
1
tIPS
V9
D Data Valid (after SCK Edge)
tv
——
25
ns
V10
D Data Hold Time (Outputs)
tho
0—
—
ns
V11
D Rise Time Inputs and Outputs
tr
——
25
ns
V12
D Fall Time Inputs and Outputs
tf
——
25
ns
1
732 678
,
×
-----------------------------
1
732 678
,
×
-----------------------------
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