參數資料
型號: MA31753
廠商: Dynex Semiconductor Ltd.
英文描述: DMA Controller (DMAC) For An MA31750 System
中文描述: DMA控制器(DMAC)對于MA31750系統(tǒng)
文件頁數: 8/30頁
文件大?。?/td> 243K
代理商: MA31753
MA31753
8/30
4.6 DMA MODE / STATUS 1
Mn
0:
1:
Channel n not masked
Channel n masked
EOTn
0:
1:
Read access only. Value can be changed by writing the channel status register.
Channel n “End of Transfer” not reached
Channel n “End of Transfer” reached
ERR
0:
1:
Read access only. Value can be changed by writing the channel status register.
No error detected
Error detected in one or more of the channels
A / B
0:
1:
1750A mode
1750B mode
BP
0:
1:
Even bus parity used
Odd bus parity used
DMAE
0:
1:
Read access only
DMA requests disabled
DMA requests enabled
Pri
000: Channel priority 0, 1, 2, 3, C
001: Channel priority 1, 2, 3, 0, C
010: Channel priority 2, 3, 0, 1, C
011: Channel priority 3, 0, 1, 2, C
100: Channel priority C, 0, 1, 2, 3
101: Channel priority C, 1, 2, 3, 0
110: Channel priority C, 2, 3, 0, 1
111: Channel priority C, 3, 0, 1, 2
5.0 DMA INSTRUCTIONS
60 DMA instructions are present in the memory or IO space between A[7:15] = 0 and A[7:15] = 1DF. Each DMA instruction
comprises of 8 16-bit words. The base address for each instruction is 8*n where n is the instruction number. The instructions are
structured as below:
Words 4, 5 and 6 are used only during area to area mode transfers. Word 6 can only be used for channels 0 and 1.
M3
M2
M1
M0
EOT3 EOT2 EOT1 EOT0
ERR A/B
BP
DMAE
Priority
D0
D15
Word number
0
1
2
3
4
5
6
7
Content
Mode/Link word
Block length
Area 1 base address
Area 1 PB, PS and AS
Area 2 base address
Area 2 PB, PS and AS
Transfer interval
Not used
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