
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
DS70657E-page 380
Preliminary
2011-2012 Microchip Technology Inc.
27.2
User ID Words
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X,
and PIC24EPXXXGP/MC20X devices contain four
User ID Words, located at addresses 0x800FF8
through 0x800FFE. The User ID Words can be used for
storing product information such as serial numbers,
system manufacturing dates, manufacturing lot
numbers and other application-specific information.
The User ID Words register map is shown in
TABLE 27-3:
USER ID WORDS REGISTER
MAP
27.3
On-Chip Voltage Regulator
All
of
the
dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X, and PIC24EPXXXGP/
MC20X devices power their core digital logic at a
nominal 1.8V. This can create a conflict for designs that
are required to operate at a higher typical voltage, such
as 3.3V. To simplify system design, all devices in the
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X,
and PIC24EPXXXGP/MC20X family incorporate an on-
chip regulator that allows the device to run its core logic
from VDD.
The regulator provides power to the core from the other
VDD pins. A low-ESR (less than 1 Ohm) capacitor (such
as tantalum or ceramic) must be connected to the VCAP
the regulator. The recommended value for the filter
FIGURE 27-1:
CONNECTIONS FOR THE
ON-CHIP VOLTAGE
REGULATOR(1,2,3)
27.4
Brown-out Reset (BOR)
The Brown-out Reset (BOR) module is based on an
internal voltage reference circuit that monitors the reg-
ulated supply voltage VCAP. The main purpose of the
BOR module is to generate a device Reset when a
brown-out condition occurs. Brown-out conditions are
generally caused by glitches on the AC mains (for
example, missing portions of the AC cycle waveform
due to bad power transmission lines, or voltage sags
due to excessive current draw when a large inductive
load is turned on).
A BOR generates a Reset pulse, which resets the
device. The BOR selects the clock source, based on
the device Configuration bit values (FNOSC<2:0> and
POSCMD<1:0>).
If an oscillator mode is selected, the BOR activates the
Oscillator Start-up Timer (OST). The system clock is
held until OST expires. If the PLL is used, the clock is
held until the LOCK bit (OSCCON<5>) is ‘1’.
Concurrently, the PWRT time-out (TPWRT) is applied
before the internal Reset is released. If TPWRT = 0 and
a crystal oscillator is being used, then a nominal delay
of TFSCM is applied. The total delay in this case is
TFSCM values.
The BOR Status bit (RCON<1>) is set to indicate that a
BOR has occurred. The BOR circuit, continues to oper-
ate while in Sleep or Idle modes and resets the device
should VDD fall below the BOR threshold voltage.
File Name
Address
Bit 23-16
Bit 15-0
FUID0
0x800FF8
—UID0
FUID1
0x800FFA
—UID1
FUID2
0x800FFC
—UID2
FUID3
0x800FFE
—UID3
Legend: — = unimplemented, read as ‘1’.
Note:
It is important for the low-ESR capacitor to
be placed as close as possible to the VCAP
pin.
Note 1: These are typical operating voltages. Refer to
VDD and VCAP.
2: It is important for the low-ESR capacitor to be
placed as close as possible to the VCAP pin.
3: Typical VCAP pin voltage = 1.8V when
VDD ≥ VDDMIN.
VDD
VCAP
VSS
dsPIC33E/PIC24E
3.3V
CEFC