參數(shù)資料
型號： M7A3PE600-FPQG208I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PQFP208
封裝： 0.50 MM PITCH, GREEN, PLASTIC, QFP-208
文件頁數(shù)： 159/168頁
文件大小： 1335K
代理商： M7A3PE600-FPQG208I
ProASIC3E Flash Family FPGAs
3- 22
Advanced v0.5
The length of time an I/O can withstand IOSH/IOSL events
depends on the junction temperature. The reliability
data below is based on a 3.3 V, 36 mA I/O setting, which
is the worst case for this type of analysis.
For example, at 110°C, the short current condition would
have to be sustained for more than three months to
cause a reliability concern. The I/O design does not
contain any short circuit protection, but such protection
would only be needed in extremely prolonged stress
conditions.
Table 3-22 Short Current Event Duration Before Failure
Temperature
Time Before Failure
–40°C
> 20 years
0°C
> 20 years
25°C
> 20 years
70°C
5 years
85°C
2 years
100°C
6 months
110°C
3 months
Table 3-23 Schmitt Trigger Input Hysteresis
Hysteresis Voltage Value (Typ) for Schmitt Mode Input Buffers
Input Buffer Configuration
Hysteresis Value (Typ)
3.3 V LVTTL/LVCMOS / PCI / PCI-X (Schmitt trigger mode)
240 mV
2.5 V LVCMOS (Schmitt trigger mode)
140 mV
1.8 V LVCMOS (Schmitt trigger mode)
80 mV
1.5 V LVCMOS (Schmitt trigger mode)
60 mV
Table 3-24 I/O Input Rise Time, Fall Time, and Related I/O Reliability1
Input Buffer
Input Rise/Fall Time (Min.)
Input Rise/Fall Time (Max.)
Reliability
LVTTL/LVCMOS (Schmitt trigger disabled)
No requirement
10 ns 2
20 years (110°C)
LVTTL/LVCMOS (Schmitt trigger enabled)
No requirement
No requirement, but input noise voltage
cannot exceed schmitt hysteresis
20 years (110°C)
HSTL/SSTL/GTL
No requirement
10 ns 2
10 years (100°C)
LVDS/BLVDS/M-LVDS/LVPECL
No requirement
10 ns 2
10 years (100°C)
Note: The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low, then the rise time and
fall time of input buffers, when Schmitt trigger is disabled, can be increased beyond the maximum value. The longer the rise/fall
times, the more susceptible the input signal is to the board noise. Actel recommends signal integrity evaluation/characterization of
the system to ensure that there is no excessive noise coupling into input signals.
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