參數資料
型號： M7A3PE600-FFG484I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PBGA484
封裝： 1 MM PITCH, FBGA-484
文件頁數： 124/168頁
文件大?。?/td> 1335K
代理商： M7A3PE600-FFG484I
ProASIC3E Flash Family FPGAs
A d v an c ed v0 . 5
2-47
Weak Pull-Up and Weak Pull-Down Resistors
ProASIC3E devices support optional weak pull-up and
pull-down resistors per I/O pin. When the I/O is pulled up,
it is connected to the VCCI of its corresponding I/O bank.
When it is pulled-down it is connected to GND. Refer to
Table 3-20 on page 3-20 for more information.
Slew Rate Control and Drive Strength
ProASIC3E devices support output slew rate control: high
and low.Actel recommends the high slew rate option to
minimize the propagation delay. This high-speed option
may introduce noise into the system if appropriate signal
integrity measures are not adopted. Selecting a low slew
rate reduces this kind of noise but adds some delays in
the system. Low slew rate is recommended when bus
transients are expected. Drive strength should also be
selected according to the design requirements and noise
immunity of the system.
The output slew rate and multiple drive strength
controls are available in LVTTL/LVCMOS 3.3 V, LVCMOS
2.5 V, LVCMOS 2.5 V / 5.0 V input, LVCMOS 1.8 V, and
LVCMOS 1.5 V. All other I/O standards have a high output
slew rate by default.
Refer to Table 2-21 for more information about the slew
rate and drive strength specification.
page 2-49 lists the default values for the above
selectable I/O attributes as well as those that are preset
for that I/O standard.
Refer to Table 2-21 for SLEW and OUT_DRIVE settings.
Table 2-22 on page 2-48 lists the I/O default attributes.
Table 2-23 on page 2-49 lists the voltages for the
supported I/O standards.
Table 2-21 I/O Standards—SLEW and Output Drive (OUT_DRIVE) Settings
I/O Standards
OUT_DRIVE (mA)
Slew
24
68
12
16
24
LVTTL/LVCMOS 3.3 V
High
Low
LVCMOS 2.5 V
High
Low
LVCMOS 2.5 V/5.0 V
High
Low
LVCMOS 1.8 V
–High
Low
LVCMOS 1.5 V
––
High
Low
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