
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17260EJ6V0UD
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Table 7-2. Capture Operation of CR00n and CR01n
External Input
Signal
Capture
Operation
TI00n Pin Input
TI01n Pin Input
Set values of ES0n1 and
ES0n0
Position of edge to be
captured
Set values of ES1n1 and
ES1n0
Position of edge to be
captured
01: Rising
00: Falling
CRC0n1 = 1
TI00n pin input
(reverse phase)
11: Both edges
(cannot be captured)
CRC0n1 bit = 0
TI01n pin input
11: Both edges
Capture operation of
CR00n
Interrupt signal
INTTM00n signal is not
generated even if value
is captured.
Interrupt signal
INTTM00n signal is
generated each time
value is captured.
Set values of ES0n1 and
ES0n0
Position of edge to be
captured
01: Rising
00: Falling
TI00n pin input
Note
11: Both edges
Capture operation of
CR01n
Interrupt signal
INTTM01n signal is
generated each time
value is captured.
Note The capture operation of CR01n is not affected by the setting of the CRC0n1 bit.
Caution
To capture the count value of the TM0n register to the CR00n register by using the phase
reverse to that input to the TI00n pin, the interrupt request signal (INTTM00n) is not generated
after the value has been captured. If the valid edge is detected on the TI01n pin during this
operation, the capture operation is not performed but the INTTM00n signal is generated as an
external interrupt signal. To not use the external interrupt, mask the INTTM00n signal.
Remarks 1. CRC0n1: See 7.3 (2) Capture/compare control register 0n (CRC0n).
ES1n1, ES1n0, ES0n1, ES0n0: See 7.3 (4) Prescaler mode register 0n (PRM0n).
2. n = 0:
PD78F0531, 78F0532, 78F0533
n = 0, 1:
PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D