參數(shù)資料
型號(hào): M74VHC1GT126DF2G
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: Noninverting Buffer / CMOS Logic Level Shifter with LSTTL−Compatible Inputs
中文描述: AHC/VHC SERIES, 1-BIT DRIVER, TRUE OUTPUT, PDSO5
封裝: LEAD FREE, SC-70, SC-88A, SOT-353, 5 PIN
文件頁數(shù): 1/6頁
文件大?。?/td> 94K
代理商: M74VHC1GT126DF2G
Semiconductor Components Industries, LLC, 2007
February, 2007 Rev. 13
1
Publication Order Number:
MC74VHC1GT126/D
MC74VHC1GT126
Noninverting Buffer /
CMOS Logic Level Shifter
with LSTTLCompatible Inputs
The MC74VHC1GT126 is a single gate noninverting 3state buffer
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
The MC74VHC1GT126 requires the 3state control input (OE) to be
set Low to place the output into the high impedance state.
The device input is compatible with TTLtype input thresholds and
the output has a full 5 V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the
input, allowing the device to be used as a logiclevel translator from
3 V CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to
3 V CMOS Logic while operating at the highvoltage power supply.
The MC74VHC1GT126 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT126 to be used to interface 5 V circuits to
3 V circuits. The output structures also provide protection when
V
CC
= 0 V. These input and output structures help prevent device
destruction caused by supply voltage input/output voltage mismatch,
battery backup, hot insertion, etc.
Features
High Speed: t
PD
= 3.5 ns (Typ) at V
CC
= 5 V
Low Power Dissipation: I
CC
= 1 A (Max) at T
A
= 25
°
C
TTLCompatible Inputs: V
IL
= 0.8 V; V
IH
= 2 V
CMOSCompatible Outputs: V
OH
> 0.8 V
CC
; V
OL
< 0.1 V
CC
@Load
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic Families
Chip Complexity: FETs = 62; Equivalent
Gates = 16
PbFree Packages are Available
Figure 1. Pinout
(Top View)
IN A
OUT Y
V
CC
OE
IN A
OUT Y
GND
OE
Figure 2. Logic Symbol
1
2
3
4
5
PIN ASSIGNMENT
1
2
3
GND
OE
IN A
4
5
V
CC
OUT Y
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
FUNCTION TABLE
L
H
X
A Input
Y Output
L
H
Z
OE Input
H
H
L
http://onsemi.com
SC88A/SOT353/SC70
DF SUFFIX
CASE 419A
TSOP5/SOT23/SC59
DT SUFFIX
CASE 483
MARKING
DIAGRAMS
1
5
1
5
1
5
W3 M
W3
M
= Device Code
= Date Code*
= PbFree Package
1
5
W3 M
M
*Date Code orientation and/or position may vary
depending upon manufacturing location.
(Note: Microdot may be in either location)
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