參數(shù)資料
型號: M74LCX16373DTR2G
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: Low−Voltage CMOS 16−Bit Transparent Latch With 5 V−Tolerant Inputs and Outputs (3−State, Non−Inverting)
中文描述: LVC/LCX/Z SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48
封裝: LEAD FREE, TSSOP-48
文件頁數(shù): 4/8頁
文件大?。?/td> 107K
代理商: M74LCX16373DTR2G
MC74LCX16373
http://onsemi.com
4
DC ELECTRICAL CHARACTERISTICS
Symbol
V
IH
Characteristic
Condition
2.3 V
V
CC
2.7 V
T
A
= 40
°
C to +85
°
C
Unit
V
Min
Max
HIGH Level Input Voltage (Note 2)
1.7
2.7 V
V
CC
3.6 V
2.0
V
IL
LOW Level Input Voltage (Note 2)
2.3 V
V
CC
2.7 V
0.7
V
2.7 V
V
CC
3.6 V
0.8
V
OH
HIGH Level Output Voltage
2.3 V
V
CC
3.6 V; I
OL
= 100 A
V
CC
0.2
V
V
CC
= 2.3 V; I
OH
= 8 mA
1.8
V
CC
= 2.7 V; I
OH
= 12 mA
2.2
V
CC
= 3.0 V; I
OH
= 18 mA
2.4
V
CC
= 3.0 V; I
OH
= 24 mA
2.2
V
OL
LOW Level Output Voltage
2.3 V
V
CC
3.6 V; I
OL
= 100 A
0.2
V
V
CC
= 2.3 V; I
OL
= 8 mA
0.6
V
CC
= 2.7 V; I
OL
= 12 mA
0.4
V
CC
= 3.0 V; I
OL
= 16 mA
0.4
V
CC
= 3.0 V; I
OL
= 24 mA
0.55
I
I
Input Leakage Current
2.3 V
V
CC
3.6 V; 0 V
V
I
5.5 V
±
5.0
A
I
OZ
3State Output Current
2.3
V
CC
3.6 V; 0V
V
O
5.5 V;
V
I
= V
IH
or V
IL
±
5.0
A
I
OFF
PowerOff Leakage Current
V
CC
= 0 V; V
I
or V
O
= 5.5 V
10
A
I
CC
Quiescent Supply Current
2.3
V
CC
3.6 V; V
I
= GND or V
CC
20
A
2.3
V
CC
3.6 V; 3.6
V
I
or V
O
5.5 V
±
20
A
I
CC
Increase in I
CC
per Input
2.3
V
CC
3.6 V; V
IH
= V
CC
0.6 V
500
A
2. These values of V
I
are used to test DC electrical characteristics only.
AC CHARACTERISTICS
t
R
= t
F
= 2.5 ns; C
L
= 50 pF; R
L
= 500
Symbol
Parameter
Waveform
T
A
= 40
°
C to +85
°
C
Unit
V
CC
= 3.3 V
±
0.3 V
C
L
= 50 pF
V
CC
= 2.7 V
C
L
= 50 pF
V
CC
= 2.5 V
±
0.2 V
C
L
= 30 pF
Min
Max
Min
Max
Min
Max
t
PLH
t
PHL
Propagation Delay
D
n
to O
n
1
1.5
1.5
5.4
5.4
1.5
1.5
5.9
5.9
1.5
1.5
6.5
6.5
ns
t
PLH
t
PHL
Propagation Delay
LE to O
n
3
1.5
1.5
5.5
5.5
1.5
1.5
6.4
6.4
1.5
1.5
6.6
6.6
ns
t
PZH
t
PZL
Output Enable Time to
High and Low Level
2
1.5
1.5
6.1
6.1
1.5
1.5
6.5
6.5
1.5
1.5
7.9
7.9
ns
t
PHZ
t
PLZ
Output Disable Time From
High and Low Level
2
1.5
1.5
6.0
6.0
1.5
1.5
6.3
6.3
1.5
1.5
7.2
7.2
ns
t
s
Setup Time, HIGH or LOW D
n
to
LE
3
2.5
2.5
3.0
ns
t
h
Hold Time, HIGH or LOW D
n
to LE
3
1.5
1.5
2.0
ns
t
w
LE Pulse Width, HIGH
3
3.0
3.0
3.5
ns
t
OSHL
t
OSLH
OutputtoOutput Skew
(Note 3)
1.0
1.0
ns
3. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGHtoLOW (t
OSHL
) or LOWtoHIGH (t
OSLH
); parameter
guaranteed by design.
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