參數(shù)資料
型號: M74HC366F1R
廠商: 意法半導體
英文描述: HEX BUS BUFFER 3-STATE HC365 NON INVERTING- HC366 INVERTING
中文描述: 六角總線緩沖器的三態(tài)非反相HC365,HC366反相
文件頁數(shù): 1/11頁
文件大?。?/td> 249K
代理商: M74HC366F1R
M54/M74HC365
M54/M74HC366
October 1992
HC365NONINVERTING-HC366INVERTING
HEX BUS BUFFER (3-STATE)
B1R
(Plastic Package)
ORDER CODES :
M54HCXXXF1R
M74HCXXXB1R
M74HCXXXM1R
M74HCXXXC1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTIONS
(top view)
DESCRIPTION
.
HIGH SPEED
t
PD
= 9 ns (TYP) AT V
CC
= 5 V
.
LOWPOWER DISSIPATION
I
CC
= 4
μ
A(MAX.) AT T
A
= 25
°
C
.
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
.
OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
|I
OH
| = I
OL
= 6 mA (MIN.)
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO6 V
.
PIN AND FUNCTION COMPATIBLE WITH
54/74LS365/366
The M54/74HC365 and the M54/74HC366 are high
speedCMOS HEX BUS BUFFER fabricated in sili-
con gate C
2
MOS technology. Theyhave the same
high speed performance of LSTTL combined with
true CMOS low power consumption.
All six buffers are controlled by the combination of
two enable inputs(G1 and G2); all outputs of these
buffers are enabled only when both G1 and G2 in-
puts are held low, under all other conditions these
output are disabled to be high-impedance.
Theseoutputs arecapableofdriving upto15LSTTL
loads. The designer has a choice of non-inverting
outputs(HC365) and inverting outputs (HC366). All
inputs are equipped with protection circuits against
staticdischarge and transient excess voltage.
HC366
HC365
1/11
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