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參數(shù)資料
| 型號： | M6XXLFXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | OTHER CLOCK GENERATOR, QCC16 |
| 封裝： | 3 X 3 MM, LEAD FREE, MO-220, QFN-24 |
| 文件頁數(shù)： | 3/17頁 |
| 文件大?。?/td> | 475K |
| 代理商： | M6XXLFXI |
MoBL Clock
M300/M600
Document Number: 001-12946 Rev. *C
Page 11 of 17
Notes
3. This parameter is configuration dependent. The specified value is for the drive level setting of [1,1].
4. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with fully loaded outputs.
AC Electrical Specifications
The AC Electrical Specifications table for M3xx/M6xx (VDD_CLKX = 1.5 V/1.8 V/2.5 V/3.0 V/3.3 V) family.
Parameter
Description
Conditions
Min
Typ
Max
Unit
FCLK
Clock Output Frequency
All clock outputs
3
–
50
MHz
FREF
Driven Reference Clock
Frequency
EXCLKIN Clock
1
–
48
MHz
DC
Output Clock Duty Cycle
Duty Cycle as defined in Figure 9
t1/t2 measured at 50% of VDD_CLKX
45
50
55
%
TRF1[4]
Output Clock Rise/Fall Time
Measured from 20% to 80% of
CLOAD = 15 pF, drive strength [00]
–
6.8
10.0
ns
TRF2[4]
Output Clock Rise/Fall Time
Measured from 20% to 80% of
CLOAD = 15 pF, drive strength [01]
–3.4
5.0
ns
TRF3[4]
Output Clock Rise/Fall Time
Measured from 20% to 80% of
CLOAD = 15 pF, drive strength [10]
–2.0
3.0
ns
TRF4[4]
Output Clock Rise/Fall Time
Measured from 20% to 80% of
CLOAD = 15 pF, drive strength [11]
–1.0
1.5
ns
TCCJ[3,4]
Cycle-to-cycle Jitter
EXCLKIN = CLKx = 48 MHz, CLOAD
= 15 pF, 3 PLLs and 1 output for each
PLL enabled, drive strength = [11]
–
150
–
ps
TLOCK[4]
PLL Lock Time
–
1
3
ms
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