參數(shù)資料
型號(hào)： M62320FP
元件分類： 微控制器/微處理器
英文描述： 8 I/O, PIA-GENERAL PURPOSE, PDSO16
封裝： 5.30 X 10.10 MM, 1.27 MM PITCH, PLASTIC, SOP-16
文件頁(yè)數(shù)： 13/13頁(yè)
文件大?。?/td> 165K
代理商： M62320FP
M62320P/FP
REJ03D0863-0300 Rev.3.00 Mar 25, 2008
Page 7 of 10
Functional Description
All parallel data I/O terminals are set to the input-state after power-on. In case any terminals need to be set to the
output state, the corresponding terminals should be set during the write mode. This setting is hold until a next setting.
In the write mode, 8 bits data can be transmitted from the I
2C BUS interface to the parallel ports continually after the
slave address and I/O setting.
In the read mode, 8 bits data can be transmitted from the parallel ports to the I
2C BUS interface continually after the
slave address setting.
In the case of a changing between the write-and read-mode, the data must be transmitted again from the starting
condition.
In a case of a data conversion from serial to parallel.
SDA
SCL
1
2
3
4
5
6
7
8
1
2345678
A1 A0
A2
11
1
00
A
P2 P1
P3
P5 P4
P6
P7
P0
A
D12 D11
D13
D15 D14
D16
D17
D10
A
D22 D21
D23
D25 D24
D26
D27
D20
A
D2X
D1X
Hi-Z
D0
to
D7
DATA
I/O setting byte
Slave address
Transmission from a master (MCU etc.)
Transmission from a slave (M62320)
Start
condition
Stop
condition
Data output
In a case of a data conversion from parallel to serial.
All I/O setting resistors are set to low (input) in the write mode, before a parallel data is read. (All I/O setting
resistors are set to the input mode after power-on).
SDA
Slave address
I/O setting byte
SCL
1
2
3
4
5
6
7
8
12345678
A1 A0
A2
11
1
00
A
P2 P1
P3
P5 P4
P6
P7
P0
A
Hi-Z
D0 to D7
output
SDA
SCL
1234567
8
A1 A0
A2
11
1
01
A
D12
D13
D15 D14
D16
D17
D11 D10
D32 D31
D33
D35 D34
A
D36
D37
D30
A
D42
D43
D45 D44
D46
D47
D41 D40
A
1234567
8
Hi-Z
D0 to D7
output
DATA
Slave address
D1X
D2X
D3X
D4X
D0 to D7
input
(example)
Transmission from a master (MCU etc.)
Transmission from a slave (M62320)
Start
condition
Start
condition
Stop
condition
Data latch
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