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參數(shù)資料
| 型號(hào)： | M62320FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8 I/O, PIA-GENERAL PURPOSE, PDSO16 |
| 封裝： | 5.30 X 10.10 MM, 1.27 MM PITCH, PLASTIC, SOP-16 |
| 文件頁數(shù)： | 11/13頁 |
| 文件大?。?/td> | 165K |
| 代理商： | M62320FP |
M62320P/FP
REJ03D0863-0300 Rev.3.00 Mar 25, 2008
Page 5 of 10
Functional Blocks
I
2C BUS Interface
The I
2C BUS interface recognizes start/stop conditions, a slave address and a write/read mode selection by receiving
SDA, SCL, CS0, CS1 and CS2 signals and then the latch pulses, dedicated to each data latch are generated.
Data Latch
This IC has 3 types of data latch: the I/O setting data latch, the input data latch and the output data latch and each latch
is controlled by the I
2C BUS interface.
I/O setting data latch
These latches set input- or output-state of each parallel data terminals (D0 to D7). They are set at the next byte after
receiving the slave address byte in the write mode from the master. In case this latch is set to high, the data is
transferred from the I
2C BUS interface to the parallel data terminals. In the opposite transmission: from the parallel
data terminals to the I
2C BUS, it is set to low.
Output data latch
In the write mode, the data from the I
2C BUS to the parallel data terminals is latched. When the master transmits
output data after a setting in write mode, the output data is taken into the latches.
Input data latch
In the read mode, the data of parallel data terminals is latched in the input data latches. The input data is taken into
the latches from the parallel data terminals on every 8th negative edge of SCL clock. The latched data is output to
the master through the sift resistor. On the output terminal assigned by the I/O setting latch, the input data latch
takes the state of the output terminal.
Parallel Input/Output Port
In case I/O setting latch is set to low (the input mode), each parallel terminal becomes hi-impedance and is able to
accept an input. In another case I/O setting latch is set to high (output mode), each parallel terminal output a data
according to the state of the output data latch.
Power on Reset
When power is turned on, each latch is reset and then the parallel data I/O terminals become hi-impedance (input mode).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M62320FP#DF5G | 制造商:Renesas Electronics Corporation 功能描述: |
| M62320GP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:8-bit I/O Expander for I2C BUS |
| M62320P | 制造商:Renesas Electronics Corporation 功能描述: |
| M62332FP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:8-bit 2ch I2C BUS D/A Converter with Buffer Amplifiers |
| M62332FP(#TF5J) | 制造商:Renesas Electronics Corporation 功能描述: |
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