參數(shù)資料
型號(hào)： M5M4V4S40CTP-12
廠商： Mitsubishi Electric Corporation
英文描述： 4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
中文描述： 4分（2 -銀行甲131072字x 16位）同步DRAM
文件頁(yè)數(shù)： 3/45頁(yè)
文件大?。?/td> 1458K
代理商： M5M4V4S40CTP-12
3
M5M4V4S40CTP-12, -15
Feb ‘97
Preliminary
MITSUBISHI LSIs
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
MITSUBISHI ELECTRIC
SDRAM (Rev. 0.3)
PIN FUNCTION
CLK
Input
Master Clock: All other inputs are referenced to the rising edge of CLK.
CKE
Input
Clock Enable: CKE controls the internal clock. When CKE is low, the
internal clock for the following cycle is disabled. CKE is also used to select
auto and self refresh. After self-refresh mode is started, CKE acts as an
asynchronous input to maintain and exit the mode.
/CS
Input
Chip Select: When /CS is high, all commands are inhibited.
/RAS, /CAS, /WE
Input
/RAS, /CAS, and /WE are used to define basic commands.
A0-8
Input
A0-8 specify the Row and Column addresses within the selected bank.
The Row Address is set by A0-8 and the Column Address is set by A0-7.
A8 is also used to indicate the precharge option. When A8 is high during
read or write command, an auto precharge is performed. When A8 is
high during a precharge command, both banks are precharged.
BA
Input
Bank Address: BA is not simply A9. BA specifies the bank to which a
command is applied. BA must be set during the ACT, PRE, READ,
and WRITE commands.
DQ0-15
Input / Output
Data In and data out are referenced to the rising edge of CLK.
DQML
Input
Lower Din(0-7) Mask; Lower Dout(0-7) Disable; When DQML is high
during burst write Din(0-7) for the current cycle is masked. When DQML
is high during burst read Dout(0-7) is disabled two cycles later.
DQMU
Input
Vdd, Vss
Power Supply
Power Supply for the memory array and peripheral circuitry.
VddQ, VssQ
Power Supply
Power Supply for the output buffers only.
Upper Din(8-15) Mask; Upper Dout(8-15) Disable; When DQMU is high
during burst write Din(8-15) for the current cycle is masked. When DQMU
is high during burst read Dout(8-15) is disabled two cycles later.
相關(guān)PDF資料
PDF描述
M5M4V4S40CTP-15 4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M5M4V4S40CTP-15 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
M5M4V64S20ATP-10 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
M5M4V64S20ATP-10L 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
M5M4V64S20ATP-12 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
M5M4V64S20ATP-8 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
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