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參數(shù)資料
| 型號(hào)： | M5M4V4S40CTP-12 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM |
| 中文描述： | 4分（2 -銀行甲131072字x 16位）同步DRAM |
| 文件頁數(shù)： | 15/45頁 |
| 文件大?。?/td> | 1458K |
| 代理商： | M5M4V4S40CTP-12 |
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M5M4V4S40CTP-12, -15
Feb ‘97
Preliminary
MITSUBISHI LSIs
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
MITSUBISHI ELECTRIC
SDRAM (Rev. 0.3)
OPERATIONAL DESCRIPTION
BANK ACTIVATE
The SDRAM has two independent banks. Each bank is activated by the ACT command with the bank
address (BA). A row inside the bank is selected by the row address A8-0. The minimum activation interval
between one bank and the opposite bank is tRRD.
PRECHARGE
The PRE command deactivates the bank indicated by BA. When both banks are active, the precharge all
command (PREA, PRE + A8=H) can be used to deactivate them at the same time. After tRP from the
precharge, an ACT command can be issued.
READ
A READ command can be issued after tRCD from bank activation (ACT). Output data is available after
the /CAS Latency from the READ, followed by (BL -1) consecutive output data (Burst Length = BL). The
start address is specified by A7-0, and the address sequence of the burst data is defined by the Burst Type. A
READ command may be applied to any active bank. This allows the row precharge time (tRP) to be hidden
behind continuous output data (in case of BL=4) by interleaving the dual banks. When A8 is high at a READ
command, the auto-precharge (READA) is performed. During READA the READ, WRITE, PRE, and ACT
commands to the same bank are inhibited until the internal precharge is complete. Internal precharge start
timing depends on /CAS Latency. The next ACT command can be issued after tRP from the precharge (PRE).
Note: READA is not allowed for FP burst length operations. The SDRAM must be manually precharged.
Bank Activation and Precharge All (BL=4, CL=3)
CLK
Command
A0-7
A8
BA
DQ
ACT
Xa
Xa
0
READ
Y
0
0
Qa0
Qa1
Qa2
Qa3
ACT
Xb
Xb
1
PRE
tRRD
tRCD
1
ACT
Xb
Xb
1
Precharge all
tRAS
tRP
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M5M4V4S40CTP-15 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM |
| M5M4V64S20ATP-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-10L | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-12 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
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