參數(shù)資料
型號: M5M4V16169DRT-7
廠商: Mitsubishi Electric Corporation
英文描述: 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
中文描述: 16MCDRAM:16米(100萬字由16位)與16K的緩存內(nèi)存(1024字由16位)的SRAM
文件頁數(shù): 62/64頁
文件大?。?/td> 737K
代理商: M5M4V16169DRT-7
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MITSUBISHI LSIs
(REV 1.0) Jul. 1998
MITSUBISHI ELECTRIC
62
*
Latency
is the number of clock
cycles required to transfer new
data from the DRAM to the Read
Buffer . Therefore, it can be
adjusted to the clock frequency of
the system.
(Latency) x (tK) should meet tCBF
min. timing requirement.
K
CMd#
CS#
RAS#
CAS#
DTD#
Ad0~11
Command
SCR
Inhibit new read or write function during these 4 clocks.
Set Command Register(2)
Output ModeTransparent
Output Mode Latched
Output Mode Registered
Command
Latency 1
Latency 2
Latency 3
Latency 4
Default
No operation
Set All WB1 Xfer Masks
Default
Ad9
Ad8 Ad7
Ad6
L
L
L
L
L
L
L
L
L
L
L
Ad5
L
L
H
H
Ad4
L
H
L
H
Ad3
L
L
H
Ad2
L
H
L
Ad1
L
L
L
L
L
L
L
L
L
L
L
Ad0
L
H
Address Input
Sequential
Interleave
Default
Default
BL=1
BL=2
BL=4
BL=8
L
H
L
L
L
H
H
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
Ad10
Ad11
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
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