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| 型號： | M52277EVB |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 19/46頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DEMO FOR MCF5227 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ColdFire® |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | MCF52277 |
| 所含物品： | 板 |
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MCF5227x ColdFire Microprocessor Data Sheet, Rev. 8
Electrical Characteristics
Freescale Semiconductor
26
DD8
Data and Data Mask Output Hold (DQS
→DQ) Relative
to DQS (DDR Write Mode)
tDQDMI
1.0
—
ns
7
DD9
Input Data Skew Relative to DQS (Input Setup)
tDVDQ
—1
ns
8
DD10 Input Data Hold Relative to DQS
tDIDQ
0.25
× SD_CLK
+0.5ns
—ns
9
DD11 DQS falling edge from SDCLK rising (output hold time) tDQLSDCH
0.5
—
ns
1 The frequency of operation is either 2x or 4x the FB_CLK frequency of operation. FlexBus and SDRAM clock operate at the
same frequency as the internal bus clock.
2 SD_CLK is one SDRAM clock in ns.
3 Pulse-width high plus pulse-width low cannot exceed minimum or maximum clock period.
4 Command output valid should be one-half the memory bus clock (SD_CLK) plus some minor adjustments for process,
temperature, and voltage variations.
5 This specification relates to the required input setup time of today’s DDR memories. The device’s output setup should be larger
than the input setup of the DDR memories. If it is not larger, then the input setup on the memory will be in violation.
MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to
MEM_DQS[1], and MEM_DATA[7:0] is relative MEM_DQS[0].
6 The first data beat will be valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats
will be valid for each subsequent DQS edge.
7 This specification relates to the required hold time of today’s DDR memories. MEM_DATA[31:24] is relative to MEM_DQS[3],
MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_DATA[7:0] is relative
MEM_DQS[0].
8 Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line
becomes valid. This input skew must include DDR memory output skew and system-level board skew (due to routing or other
factors).
9 Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line becomes
invalid.
Table 15. DDR Timing Specifications (continued)
Num
Characteristic
Symbol
Min
Max
Unit
Notes
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