- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄296402 > M50FW080NB5T (意法半導(dǎo)體) 8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory PDF資料下載
參數(shù)資料
| 型號： | M50FW080NB5T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory |
| 中文描述： | 8兆1兆× 8，統(tǒng)一座3V電源閃存固件集線器 |
| 文件頁數(shù)： | 5/47頁 |
| 文件大?。?/td> | 765K |
| 代理商： | M50FW080NB5T |
第1頁第2頁第3頁第4頁當前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁
13/47
M50FW080
equipment for faster factory programming. Only a
subset of the features available to the Firmware
Hub (FWH) Interface are available; these include
all the Commands but exclude the Security fea-
tures and other registers.
The following operations can be performed using
the appropriate bus cycles: Bus Read, Bus Write,
Output Disable and Reset.
When the Address/Address Multiplexed (A/A Mux)
Interface is selected all the blocks are unprotect-
ed. It is not possible to protect any blocks through
this interface.
Bus Read. Bus Read operations are used to out-
put the contents of the Memory Array, the Elec-
tronic Signature and the Status Register. A valid
Bus Read operation begins by latching the Row
Address and Column Address signals into the
memory using the Address Inputs, A0-A10, and
the Row/Column Address Select RC. Then Write
Enable (W) and Interface Reset (RP) must be
High, VIH, and Output Enable, G, Low, VIL, in order
to perform a Bus Read operation. The Data Inputs/
Outputs will output the value, see Figure 14. and
Table 24., for details of when the output becomes
valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by latching the Row Address and Column
Address signals into the memory using the Ad-
dress Inputs, A0-A10, and the Row/Column Ad-
dress Select RC. The data should be set up on the
Data Inputs/Outputs; Output Enable, G, and Inter-
face Reset, RP, must be High, VIH and Write En-
able, W, must be Low, VIL. The Data Inputs/
Outputs are latched on the rising edge of Write En-
able, W. See Figure 15. and Table 25., for details
of the timing requirements.
Output Disable. The data outputs are high-im-
pedance when the Output Enable, G, is at VIH.
Reset. During Reset mode all internal circuits are
switched off, the memory is deselected and the
outputs are put in high-impedance. The memory is
in Reset mode when RP is Low, VIL. RP must be
held Low, VIL for tPLPH. If RP is goes Low, VIL, dur-
ing a Program or Erase operation, the operation is
aborted and the memory cells affected no longer
contain valid data; the memory can take up to tPL-
RH to abort a Program or Erase operation.
Table 4. FWH Bus Read Field Definitions
Clock
Cycle
Number
Clock
Cycle
Count
Field
FWH0-
FWH3
Memory
I/O
Description
1
START
1101b
I
On the rising edge of CLK with FWH4 Low, the contents of
FWH0-FWH3 indicate the start of a FWH Read cycle.
2
1
IDSEL
XXXX
I
Indicates which FWH Flash Memory is selected. The value
on FWH0-FWH3 is compared to the IDSEL strapping on the
FWH Flash Memory pins to select which FWH Flash
Memory is being addressed.
3-9
7
ADDR
XXXX
I
A 28-bit address phase is transferred starting with the most
significant nibble first.
10
1
MSIZE
0000b
I
Always 0000b (only single byte transfers are supported).
11
1
TAR
1111b
I
The host drives FWH0-FWH3 to 1111b to indicate a
turnaround cycle.
12
1
TAR
1111b
(float)
O
The FWH Flash Memory takes control of FWH0-FWH3
during this cycle.
13-14
2
WSYNC
0101b
O
The FWH Flash Memory drives FWH0-FWH3 to 0101b
(short wait-sync) for two clock cycles, indicating that the data
is not yet available. Two wait-states are always included.
15
1
RSYNC
0000b
O
The FWH Flash Memory drives FWH0-FWH3 to 0000b,
indicating that data will be available during the next clock
cycle.
16-17
2
DATA
XXXX
O
Data transfer is two CLK cycles, starting with the least
significant nibble.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M50FW080NB5TG | 8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory |
| M524-012.8M | TCVCXO, CLOCK, 12.8 MHz, CMOS OUTPUT |
| M504-020.0M | TCVCXO, CLOCK, 20 MHz, CMOS OUTPUT |
| M504-012.8M | TCVCXO, CLOCK, 12.8 MHz, CMOS OUTPUT |
| M614-020.0M | TCVCXO, CLOCK, 20 MHz, CMOS OUTPUT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M50FW080NB5TG | 功能描述:閃存 SERIAL FLASH RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| M50FW080NB5TP | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory |
| M50G1041 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Multilayer Ceramic Capacitors |
| M50G1041-F | 制造商:CDE 制造商全稱:Cornell Dubilier Electronics 功能描述:Multilayer Ceramic Capacitors COG (NPO). X7R & Z5U Capacitors |
| M50G104J1 | 功能描述:CAP CER 0.1UF 100V 5% RADIAL RoHS:否 類別:電容器 >> 陶瓷 系列:M50 標準包裝:4,000 系列:- 電容:1000pF 電壓 - 額定:50V 容差:±10% 溫度系數(shù):X7R 安裝類型:表面貼裝，MLCC 工作溫度:-55°C ~ 125°C 應(yīng)用:自動 額定值:AEC-Q200 封裝/外殼:0805（2012 公制） 尺寸/尺寸:0.079" L x 0.047" W（2.00mm x 1.20mm） 高度 - 座高（最大）:- 厚度（最大）:- 引線間隔:- 特點:- 包裝:帶卷 (TR) 引線型:- |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。