參數(shù)資料
型號(hào)： M50FW016N5G
廠商： 意法半導(dǎo)體
英文描述： 16 Mbit 2Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory
中文描述： 16兆位的2Mb × 8，統(tǒng)一座3V電源閃存固件集線器
文件頁(yè)數(shù)： 17/45頁(yè)
文件大小： 673K
代理商： M50FW016N5G
M50FW016
24/45
Table 13. Lock Register Bit Definitions
Note: 1. Applies to Top Block Lock Register (T_BLOCK_LK) and Top Block [-1] Lock Register (T_MINUS01_LK) to Top Block [-31] Lock
Register (T_MINUS31_LK).
Table 14. General Purpose Input Register Definition
Note: 1. Applies to the General Purpose Input Register (FGPI_REG).
Bit
Bit Name
Value
Function
7-3
Reserved
2
Read-Lock
‘1’
Bus Read operations in this Block always return 00h.
‘0’
Bus read operations in this Block return the Memory Array contents. (Default
value).
1
Lock-Down
‘1’
Changes to the Read-Lock bit and the Write-Lock bit cannot be performed. Once a
‘1’ is written to the Lock-Down bit it cannot be cleared to ‘0’; the bit is always reset
to ‘0’ following a Reset (using RP or INIT) or after power-up.
‘0’
Read-Lock and Write-Lock can be changed by writing new values to them. (Default
value).
0Write-Lock
‘1’
Program and Block Erase operations in this Block will set an error in the Status
Register. The memory contents will not be changed. (Default value).
‘0’
Program and Block Erase operations in this Block are executed and will modify the
Block contents.
Bit
Bit Name
Value
Function
7-5
Reserved
4
FGPI4
‘1’
Input Pin FGPI4 is at VIH
‘0’
Input Pin FGPI4 is at VIL
3
FGPI3
‘1’
Input Pin FGPI3 is at VIH
‘0’
Input Pin FGPI3 is at VIL
2
FGPI2
‘1’
Input Pin FGPI2 is at VIH
‘0’
Input Pin FGPI2 is at VIL
1
FGPI1
‘1’
Input Pin FGPI1 is at VIH
‘0’
Input Pin FGPI1 is at VIL
0
FGPI0
‘1’
Input Pin FGPI0 is at VIH
‘0’
Input Pin FGPI0 is at VIL
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