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參數(shù)資料
| 型號： | M50FLW080AN5T |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | PROM |
| 英文描述： | 1M X 8 FLASH 3V PROM, 11 ns, PDSO40 |
| 封裝： | 10 X 20 MM, PLASTIC, TSOP-40 |
| 文件頁數(shù)： | 3/53頁 |
| 文件大?。?/td> | 945K |
| 代理商： | M50FLW080AN5T |
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M50FLW080A, M50FLW080B
changed during Program or Erase Suspend, and
care should be taken to avoid this.
Write Protect (WP). The Write Protect input is
used to prevent the Main Blocks (Blocks 0 to 14)
from being changed. When Write Protect, WP, is
driven Low, VIL, Program and Erase operations in
the Main Blocks have no effect, regardless of the
state of the Lock Register. When Write Protect,
WP, is driven High, VIH, the protection of the Block
or Sector is determined by the Lock Registers. The
state of Write Protect, WP, does not affect the pro-
tection of the Top Block (Block 15). For details,
see APPENDIX A..
Write Protect, WP, must be set prior to a Program
or Erase operation is initiated, and must not be
changed until the operation has completed other-
wise unpredictable results may occur. Similarly,
unpredictable behavior is possible if WP is
changed during Program or Erase Suspend, and
care should be taken to avoid this.
Reserved for Future Use (RFU). Reserved
for
Future Use (RFU). These pins do not presently
have assigned functions. They must be left discon-
nected, except for ID0 and ID1 (when in LPC
mode) which can be left connected. The electrical
characteristics for these signals are as described
in the “Identification Inputs (ID0-ID3).” section.
Address/Address Multiplexed (A/A Mux)
Signal Descriptions
Address Inputs (A0-A10). The Address Inputs
are used to set the Row Address bits (A0-A10) and
the Column Address bits (A11-A19). They are
latched during any bus operation by the Row/Col-
umn Address Select input, RC.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs hold the data that is to be written to
or read from the memory. They output the data
stored at the selected address during a Bus Read
operation. During Bus Write operations they carry
the commands that are sent to the Command In-
terface of the internal state machine. The Data In-
puts/Outputs, DQ0-DQ7, are latched during a Bus
Write operation.
Output Enable (G). The Output Enable signal, G,
controls the output buffers during a Bus Read op-
eration.
Write Enable (W). The Write Enable signal, W,
controls the Bus Write operation of the Command
Interface.
Row/Column Address Select (RC). The
Row/
Column Address Select input selects whether the
Address Inputs are to be latched into the Row Ad-
dress bits (A0-A10) or the Column Address bits
(A11-A19). The Row Address bits are latched on
the falling edge of RC whereas the Column Ad-
dress bits are latched on its rising edge.
Supply Signal Descriptions
The Supply Signals are the same for both interfac-
es.
VCC Supply Voltage. The VCC Supply Voltage
supplies the power for all operations (read, pro-
gram, erase, etc.).
The Command Interface is disabled when the VCC
Supply Voltage is less than the Lockout Voltage,
VLKO. This is to prevent Bus Write operations from
accidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time, the operation aborts, and the memory
contents that were being altered will be invalid. Af-
ter VCC becomes valid, the Command Interface is
reset to Read mode.
A 0.1F capacitor should be connected between
the VCC Supply Voltage pins and the VSS Ground
pin to decouple the current surges from the power
supply. Both VCC Supply Voltage pins must be
connected to the power supply. The PCB track
widths must be sufficient to carry the currents re-
quired during program and erase operations.
VPP Optional Supply Voltage. The VPP Optional
Supply Voltage pin is used to select the Fast Pro-
gram (see the Quadruple Byte Program command
description in A/A Mux interface and the Double/
Quadruple Byte Program command description in
FWH mode) and Fast Erase options of the memo-
ry.
When VPP = VCC, program and erase operations
take place as normal. When VPP = VPPH, Fast Pro-
gram and Erase operations are used. Any other
voltage input to VPP will result in undefined behav-
ior, and should not be used.
VPP should not be set to VPPH for more than
80 hours during the life of the memory.
VSS Ground. VSS is the reference for all the volt-
age measurements.
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| M50FLW080AN5TG | 功能描述:IC FLASH 8MBIT 33MHZ 40TSOP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:移動 SDRAM 存儲容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| M50FLW080AN5TP | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW080ANB5 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW080ANB5G | 功能描述:閃存 8Mbit 3V Firmwre Hub Low pin-count flash RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| M50FLW080ANB5P | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
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