參數(shù)資料
型號(hào)： M50FLW080AN5G
廠商： STMICROELECTRONICS
元件分類(lèi)： PROM
英文描述： 1M X 8 FLASH 3V PROM, 11 ns, PDSO40
封裝： 10 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-40
文件頁(yè)數(shù)： 24/64頁(yè)
文件大?。?/td> 534K
代理商： M50FLW080AN5G
Command interface
M50FLW080A, M50FLW080B
Table 13.
Commands
Command
Cyc
le
Bus operations(1)
1st
2nd
3rd
4th
5th
Addr Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Read Memory Array(2),(3),(4)
1+
X
FFh
Read
Addr
Read
Data
(Read
Addr2)
(Read
Data2)
(Read
Addr3)
(Read
Data3)
(Read
Addr4)
(Read
Data4)
Read Status Register(5),(3)
1+
X
70h
X
Status
Reg
(X)
(Status
Reg)
(X)
(Status
Reg)
(X)
(Status
Reg)
Read Electronic Signature(3)
1+
X
90h or
98h
Sig
Addr
Signat
ure
(Sig
Addr)
(Signat
ure)
(Sig
Addr)
(Signatu
re)
(Sig
Addr)
(Signat
ure)
Program / Multiple Byte
program (FWH)(6),(7),(4)
2X
40h or
10h
Prog
Addr
Prog
Data
Quadruple Byte Program
(A/A Mux)(6),(8)
5X
30h
A1
Prog
Data1
A2
Prog
Data2
A3
Prog
Data3
A4
Prog
Data4
Chip Erase(6)
2
X
80h
X
10h
Block Erase(6)
2X
20h
BA
D0h
Sector Erase(6)
2X
32h
SA
D0h
Clear Status Register(9)
1X
50h
Program/Erase suspend(10)
1X
B0h
Program/Erase resume(11)
1X
D0h
Invalid reserved(12)
1X
00h
1X
01h
1X
60h
1X
2Fh
1X
C0h
1.
For all commands: the first cycle is a Write. For the first three commands (Read Memory, Read Status Register, Read
Electronic Signature), the second and next cycles are READ. For the remaining commands, the second and next cycles
are WRITE.
BA = Any address in the Block, SA = Any address in the Sector. X = Don’t Care, except that A22=1 (for FWH or LPC
mode), and A21 and A20 are set according to the rules shown in Table 5 (for LPC mode)
2.
After a Read Memory Array command, read the memory as normal until another command is issued.
3.
“1+” indicates that there is one write cycle, followed by any number of read cycles.
4.
Configuration registers are accessed directly without using any specific command code. A single Bus Write or Bus Read
Operation is all that is needed.
5.
After a Read Status Register command, read the Status Register as normal until another command is issued.
6.
After the erase and program commands read the Status Register until the command completes and another command is
issued.
7.
Multiple Byte Program PA= start address, A0 (Double Byte Program) A0 and A1 (Quadruple Byte Program) are Don`t
Care. PD is two or four Bytes depending on Msize code.
8.
Addresses A1, A2, A3 and A4 must be consecutive addresses, differing only in address bits A0 and A1.
9.
After the Clear Status Register command bits SR1, SR3, SR4 and SR5 in the Status Register are reset to ‘0’.
10. While an operation is being Program/Erase Suspended, the Read Memory Array, Read Status Register, Program (during
Erase Suspend) and Program/Erase Resume commands can be issued.
11. The Program/Erase Resume command causes the Program/Erase suspended operation to resume. Read the Status
Register until the Program/Erase Controller completes and the memory returns to Read Mode.
12. Do not use Invalid or Reserved commands.
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